Espressif's ESP32-C2 (ordered under the ESP8684H1/H2/H4 series) integrates a 120 MHz 32-bit RISC-V core, 272 KB SRAM, 576 KB ROM, and 1 MB, 2 MB, or 4 MB of stacked Quad SPI flash in a tiny 4×4 mm QFN-24 package designed to replace legacy ESP8266/2.4 GHz modules at minimal BOM cost. Supporting 2.4 GHz Wi-Fi 4 (802.11b/g/n) and Bluetooth 5 LE, its GPIO Matrix routes 2× UART, SPI2 (FSPI), I2C0, and 6× LEDC PWM channels across 14 exposed GPIOs (GPIO0–GPIO10, GPIO18–GPIO20; no native USB). Five 12-bit SAR ADC1 channels cover GPIO0–GPIO4 across a 3.0 V–3.6 V supply with 26 MHz or 40 MHz crystal support. All I/Os are strictly 3.3 V non-5V-tolerant, and GPIO8 must stay HIGH when pulling GPIO9 LOW for UART0 Download Boot.
All ESP8684 (ESP32-C2) silicon variants integrate Quad SPI flash inside the QFN-24 package; flash pins are not bonded externally.
Add the peripherals you need and plan the pin assignments
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | ANT | special | ANT |
[INFO] 2.4 GHz 50Ω RF antenna port
Dedicated 2.4 GHz RF input/output for Wi-Fi 4 and Bluetooth 5 LE. Requires an external 50Ω matching network.
2.4 GHz RF antenna input/output pin
|
| 2 | VDDA3P3 | power | VDDA3P3 |
Analog & PA/LNA power supply (3.0V–3.6V, 3.3V nominal)
|
| 3 | VDDA3P3 | power | VDDA3P3 |
Analog & PA/LNA power supply (3.0V–3.6V, 3.3V nominal)
|
| 4 | GPIO0 | mixed | GPIO0 ADC1_CH0 XTAL_32K_P LEDC_CH0 |
[INFO] Brief low-level glitch possible during power-up reset
May experience a brief low-level pulse during initial power-on before I/O mux latches stabilize.
RTC/Digital GPIO0, 12-bit ADC1_CH0, and optional 32.768 kHz crystal P (3.3V max, NOT 5V tolerant)
|
| 5 | GPIO1 | mixed | GPIO1 ADC1_CH1 XTAL_32K_N LEDC_CH1 |
[INFO] Brief low-level glitch possible during power-up reset
May experience a brief low-level pulse during initial power-on before I/O mux latches stabilize.
RTC/Digital GPIO1, 12-bit ADC1_CH1, and optional 32.768 kHz crystal N (3.3V max, NOT 5V tolerant)
|
| 6 | GPIO2 | mixed | GPIO2 ADC1_CH2 FSPIQ LEDC_CH2 |
RTC/Digital GPIO2, 12-bit ADC1_CH2, and direct IO_MUX SPI2 MISO (FSPIQ) (3.3V max, NOT 5V tolerant)
|
| 7 | CHIP_EN CHIP_PU | reset | CHIP_EN |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND) for clean power-on reset timing.
High-enable / active-low chip reset input (CHIP_EN / EN)
|
| 8 | GPIO3 | mixed | GPIO3 ADC1_CH3 LEDC_CH3 |
[INFO] Brief low-level glitch possible during power-up reset
May experience a brief low-level pulse during initial power-on before I/O mux latches stabilize.
RTC/Digital GPIO3 and 12-bit ADC1_CH3 (3.3V max, NOT 5V tolerant)
|
| 9 | GPIO4 | mixed | GPIO4 ADC1_CH4 FSPIHD MTMS LEDC_CH4 |
[INFO] Dedicated JTAG MTMS pin (no native USB JTAG on ESP32-C2)
Used as JTAG TMS when debugging via external JTAG probe; freely usable for ADC1_CH4 or GPIO otherwise.
RTC/Digital GPIO4, 12-bit ADC1_CH4, FSPIHD, and JTAG MTMS (3.3V max, NOT 5V tolerant)
|
| 10 | GPIO5 | digital | GPIO5 FSPIWP MTDI LEDC_CH5 |
[INFO] Dedicated JTAG MTDI pin & brief power-up low glitch
Digital-only on ESP32-C2 (ADC1 spans GPIO0–GPIO4 only). Used for JTAG TDI if hardware JTAG is active.
RTC/Digital GPIO5 (digital only — no ADC on ESP32-C2), FSPIWP, and JTAG MTDI
|
| 11 | VDD3P3_RTC | power | VDD3P3_RTC |
RTC and low-power digital I/O power supply domain for GPIO0–GPIO5 (3.0V–3.6V)
|
| 12 | GPIO6 | digital | GPIO6 FSPICLK MTCK LEDC_CH0 |
[INFO] Dedicated JTAG MTCK pin when hardware JTAG debugging is used
Freely usable for direct IO_MUX SPI2 SCK (FSPICLK), I2C, or GPIO when JTAG is unused.
Digital GPIO6, direct IO_MUX SPI2 SCK (FSPICLK), and JTAG MTCK (3.3V max, NOT 5V tolerant)
|
| 13 | GPIO7 | digital | GPIO7 FSPID MTDO LEDC_CH1 |
[INFO] Dedicated JTAG MTDO pin when hardware JTAG debugging is used
Freely usable for direct IO_MUX SPI2 MOSI (FSPID), I2C, or GPIO when JTAG is unused.
Digital GPIO7, direct IO_MUX SPI2 MOSI (FSPID), and JTAG MTDO (3.3V max, NOT 5V tolerant)
|
| 14 | GPIO8 | digital | GPIO8 LEDC_CH2 |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — MUST be HIGH for Download Boot)
Sampled at reset with no internal pull-up. Entering UART0 Download Boot (GPIO9=LOW) strictly requires GPIO8=HIGH (GPIO8=0 & GPIO9=0 is an invalid boot state!). Add a 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Digital GPIO8 (Download Boot gate & ROM UART0 print strapping pin)
|
| 15 | GPIO9 | digital | GPIO9 LEDC_CH3 |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=UART0 Download Boot)
Sampled at reset with internal weak pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters UART0 Download Boot (ESP32-C2 has no native USB). Avoid external loads holding GPIO9 low at power-up.
Digital GPIO9 (BOOT button strapping pin with internal weak pull-up)
|
| 16 | GPIO10 | digital | GPIO10 FSPICS0 LEDC_CH4 |
Digital GPIO10 and direct IO_MUX SPI2 CS0 (FSPICS0) (3.3V max, NOT 5V tolerant)
|
| 17 | VDD3P3_CPU | power | VDD3P3_CPU |
Digital CPU and I/O power supply domain for GPIO6–GPIO20 (3.0V–3.6V)
|
| 18 | GPIO18 | digital | GPIO18 LEDC_CH5 |
Digital GPIO18 (general-purpose I/O — note ESP32-C2 has no native USB peripheral)
|
| 19 | U0RXD GPIO19 | digital | GPIO19 U0RXD LEDC_CH0 |
[INFO] Primary UART0 RX input for ROM firmware flashing & console
Because ESP32-C2 omits native USB, UART0 (GPIO19 RX / GPIO20 TX) is the sole serial firmware download interface.
Digital GPIO19 and default UART0 RX (U0RXD) (3.3V max, NOT 5V tolerant)
|
| 20 | U0TXD GPIO20 | digital | GPIO20 U0TXD LEDC_CH1 |
[INFO] Primary UART0 TX output for ROM firmware flashing & boot log
Emits ROM boot log messages at reset unless suppressed via GPIO8. Serves as the sole serial flashing TX line.
Digital GPIO20 and default UART0 TX (U0TXD) (3.3V max, NOT 5V tolerant)
|
| 21 | VDDA | power | VDDA |
Analog PLL and crystal oscillator power supply (3.0V–3.6V)
|
| 22 | XTAL_N | clock | XTAL_N |
[INFO] 26 MHz or 40 MHz RF crystal negative pin (frequency not auto-detected)
Supports 26 MHz or 40 MHz ±10 ppm reference crystal. Crystal frequency is not stored in eFuse; ROM defaults to 40 MHz, so 26 MHz designs must configure CONFIG_XTAL_FREQ_26 in firmware.
External 26 MHz or 40 MHz crystal oscillator negative output
|
| 23 | XTAL_P | clock | XTAL_P |
[INFO] 26 MHz or 40 MHz RF crystal positive pin (frequency not auto-detected)
Supports 26 MHz or 40 MHz ±10 ppm reference crystal. Official Espressif ESP8684 modules integrate a 26 MHz crystal inside the RF shield.
External 26 MHz or 40 MHz crystal oscillator positive input
|
| 24 | VDDA | power | VDDA |
Analog PLL and crystal oscillator power supply (3.0V–3.6V)
|
| 25 | GND | ground | GND |
Central exposed thermal and electrical ground pad (0V)
|