Integrating ESP32-S2FH4 (4 MB flash) or ESP32-S2FN4R2 (4 MB flash + 2 MB PSRAM) in a 15.4×20.5 mm (PCB antenna) or 15.4×15.4 mm (MINI-2U U.FL) 0.85 mm LGA package, ESP32-S2-MINI-2 exposes up to 37 GPIOs (36 on -N4R2 where Pin 26 IO26 is occupied by internal PSRAM). Pin-for-pin compatible with ESP32-S2-MINI-1.
Silicon IC:ESP32-S2Boards / Modules:ESP32-S2-SOLO-2Also known as:ESP32-S2-MINI-2UESP32-S2-MINI-2-N4ESP32-S2-MINI-2-N4R2ESP32-S2-MINI-1
Onboard Peripherals & Internal Signals
In-Package 4 MB Flash (+ 2 MB PSRAM on -N4R2)QSPI
Chip Pad: GPIO29
Internal SPI0/1 flash on GPIO27–32 (plus GPIO26 SPICS1 on -N4R2)
Leave Pin 26 floating if designing for -N4R2 PSRAM compatibility.
Pin Assignment Planner
Add the peripherals you need and plan the pin assignments
Full Pin Reference (46 Pins)
Pin #
Label
Type
Functions
Warnings & Notes
1
GND
ground
GND
Module system ground (0V)
2
GND
ground
GND
Module system ground (0V)
3
3V3
power
3V3
[CAUTION] 3.0V–3.6V supply only (>=500 mA current capability + 10 µF & 0.1 µF decoupling)
Wi-Fi TX bursts draw high peak current. Exceeding 3.6V permanently damages the SoC and onboard flash.
Main 3.3V module power supply input (3.0V–3.6V; >=500 mA regulator recommended)
Reconfiguring GPIO19/GPIO20 as digital I/O disconnects native USB CDC/DFU.
General-purpose 3.3V GPIO20 (NOT 5V tolerant)
25
IO21
GPIO21
digital
GPIO21
General-purpose 3.3V GPIO21 (NOT 5V tolerant)
26
IO26
GPIO26
digital
GPIO26SPICS1
[CAUTION] SPICS1 — reserved for PSRAM CE# on -R2 / -FN4R2 / -N4R2 variants
Usable as GPIO26 only on non-PSRAM variants; internally bonded to 2 MB PSRAM CE# on PSRAM-equipped chips and modules.
[DANGER] Reserved for internal 2 MB PSRAM CE# on -N4R2 variants — leave unconnected on -N4R2!
Available as GPIO26 ONLY on non-PSRAM -N4 modules. On ESP32-S2-MINI-2-N4R2 / MINI-2U-N4R2, Pin 26 is internally wired to PSRAM SPICS1.
General-purpose 3.3V GPIO26 (NOT 5V tolerant)
27
NC
nc
—
No internal connection — leave floating on host PCB
28
IO33
GPIO33
digital
GPIO33
General-purpose 3.3V GPIO33 (NOT 5V tolerant)
29
IO34
GPIO34
digital
GPIO34
General-purpose 3.3V GPIO34 (NOT 5V tolerant)
30
GND
ground
GND
Module system ground (0V)
31
IO35
GPIO35
digital
GPIO35
General-purpose 3.3V GPIO35 (NOT 5V tolerant)
32
IO36
GPIO36
digital
GPIO36
General-purpose 3.3V GPIO36 (NOT 5V tolerant)
33
IO37
GPIO37
digital
GPIO37
General-purpose 3.3V GPIO37 (NOT 5V tolerant)
34
IO38
GPIO38
digital
GPIO38
General-purpose 3.3V GPIO38 (NOT 5V tolerant)
35
IO39
GPIO39
digital
GPIO39MTCK
General-purpose 3.3V GPIO39 (NOT 5V tolerant)
36
IO40
GPIO40
digital
GPIO40MTDO
General-purpose 3.3V GPIO40 (NOT 5V tolerant)
37
IO41
GPIO41
digital
GPIO41MTDI
General-purpose 3.3V GPIO41 (NOT 5V tolerant)
38
IO42
GPIO42
digital
GPIO42MTMS
General-purpose 3.3V GPIO42 (NOT 5V tolerant)
39
TXD0
GPIO43
digital
GPIO43U0TXD
General-purpose 3.3V GPIO43 (NOT 5V tolerant)
40
RXD0
GPIO44
digital
GPIO44U0RXD
General-purpose 3.3V GPIO44 (NOT 5V tolerant)
41
IO45
GPIO45
digital
GPIO45
[DANGER] VDD_SPI flash voltage strap (weak pull-down: LOW=3.3V, HIGH=1.8V)
Pulling GPIO45 HIGH at reset switches VDD_SPI to 1.8V, preventing 3.3V flash/PSRAM parts from booting.
General-purpose 3.3V GPIO45 (NOT 5V tolerant)
42
GND
ground
GND
Module system ground (0V)
43
GND
ground
GND
Module system ground (0V)
44
IO46
GPIO46
digital
GPIO46
[CAUTION] Input-only strapping pin (fixed internal pull-down; NO output driver!)
On ESP32-S2, GPIO46 has no output buffer and cannot drive signals high or low. Also sampled at reset for boot mode & ROM log printing (keep LOW at reset).
Input-only strapping pin GPIO46 (no output driver, internal pull-down)
45
EN
CHIP_PU
reset
CHIP_PU
[CAUTION] Active-HIGH chip enable / reset — never leave floating
Add an external 10 kΩ pull-up to 3.3V and 1 µF capacitor to GND.
Active-HIGH chip enable / reset input (EN / CHIP_PU)