Integrating Espressif's ESP32-C3FH4/FN4 SiP (160 MHz 32-bit RISC-V core, 400 KB SRAM, and 4 MB in-package Quad SPI flash) with a 40 MHz crystal, the ESP32-C3-MINI-1 shrinks 2.4 GHz Wi-Fi 4 and Bluetooth 5.0 LE connectivity into 13.2×16.6 mm (PCB antenna) and 13.2×12.5 mm (MINI-1U external antenna) 0.8 mm LGA footprints shared across Espressif's MINI family. Fifteen exposed 3.3 V GPIOs (IO0–IO10, IO18–IO21) support GPIO Matrix routing for UART, SPI2, I2C0, I2S0, TWAI, LEDC PWM, and native USB Serial/JTAG (IO18/IO19). Five 12-bit SAR ADC1 inputs cover IO0–IO4 across a 3.0 V–3.6 V rail. All I/Os are strictly non-5V-tolerant, and IO8/IO9 boot strapping rules apply.
Quad SPI XIP flash is integrated inside the QFN-32 SiP package under the RF shield.
Add the peripherals you need and plan the pin assignments
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | GND | ground | GND |
Module system ground (0V)
|
| 2 | GND | ground | GND |
Module system ground (0V)
|
| 3 | 3V3 | power | 3V3 |
[CAUTION] 3.0V–3.6V supply only (>=500 mA regulator + 10 µF & 0.1 µF bypass caps near Pin 3)
Wi-Fi transmit bursts require low-impedance 3.3V power delivery. Exceeding 3.6V permanently damages the SoC.
Main 3.3V module power supply input (3.0V–3.6V; >=500 mA current capability recommended)
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| 4 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 5 | IO2 GPIO2 | mixed | GPIO2 ADC1_CH2 FSPIQ LEDC_CH2 |
[CAUTION] Boot strapping pin (must be HIGH during Download Boot)
Sampled at reset with no internal pull-up enabled. Keep GPIO2 HIGH (or add a 10 kΩ pull-up) when entering Joint Download Boot via GPIO9=LOW to prevent unintended glitch modes.
RTC/Digital GPIO2, 12-bit ADC1_CH2, direct IO_MUX SPI2 MISO (FSPIQ), and boot strapping pin
|
| 6 | IO3 GPIO3 | mixed | GPIO3 ADC1_CH3 LEDC_CH3 |
RTC/Digital GPIO3 and 12-bit ADC1_CH3 (3.3V max, NOT 5V tolerant)
|
| 7 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 8 | EN CHIP_PU | reset | CHIP_EN |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND) to meet power-on reset timing.
High-enable / active-low chip reset input (CHIP_EN / EN)
|
| 9 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 10 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 11 | GND | ground | GND |
Module system ground (0V)
|
| 12 | IO0 GPIO0 | mixed | GPIO0 ADC1_CH0 XTAL_32K_P LEDC_CH0 |
RTC/Digital GPIO0, 12-bit ADC1_CH0, and 32.768 kHz crystal P (3.3V max, NOT 5V tolerant)
|
| 13 | IO1 GPIO1 | mixed | GPIO1 ADC1_CH1 XTAL_32K_N LEDC_CH1 |
RTC/Digital GPIO1, 12-bit ADC1_CH1, and 32.768 kHz crystal N (3.3V max, NOT 5V tolerant)
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| 14 | GND | ground | GND |
Module system ground (0V)
|
| 15 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 16 | IO10 GPIO10 | digital | GPIO10 FSPICS0 LEDC_CH4 |
Digital GPIO10 and direct IO_MUX SPI2 CS0 (FSPICS0) (3.3V max, NOT 5V tolerant)
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| 17 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 18 | IO4 GPIO4 | mixed | GPIO4 ADC1_CH4 FSPIHD MTMS LEDC_CH4 |
[INFO] Dedicated JTAG MTMS pin if external JTAG probe is enabled
Free for ADC1_CH4, SPI2, or general GPIO when debugging over native USB Serial/JTAG (GPIO18/GPIO19).
RTC/Digital GPIO4, 12-bit ADC1_CH4, FSPIHD, and JTAG MTMS (3.3V max, NOT 5V tolerant)
|
| 19 | IO5 GPIO5 | mixed | GPIO5 ADC2_CH0 FSPIWP MTDI LEDC_CH5 |
[CAUTION] ADC2_CH0 affected by silicon errata [ADC-183] & Wi-Fi arbitration — prefer GPIO0–GPIO4 for analog
Hardware errata [ADC-183] disables continuous/DMA ADC2 operation on ESP32-C3, and ADC2 is shared with the Wi-Fi radio. Safe as a standard digital GPIO; use GPIO0–GPIO4 (ADC1) for reliable analog reads.
RTC/Digital GPIO5, ADC2_CH0 (see errata), FSPIWP, and JTAG MTDI
|
| 20 | IO6 GPIO6 | digital | GPIO6 FSPICLK MTCK LEDC_CH0 |
[INFO] Dedicated JTAG MTCK pin if external JTAG probe is enabled
Completely free for high-speed IO_MUX SPI2 SCK, I2C, or GPIO when using native USB Serial/JTAG.
Digital GPIO6, direct IO_MUX SPI2 SCK (FSPICLK), and JTAG MTCK (3.3V max, NOT 5V tolerant)
|
| 21 | IO7 GPIO7 | digital | GPIO7 FSPID MTDO LEDC_CH1 |
[INFO] Dedicated JTAG MTDO pin if external JTAG probe is enabled
Completely free for high-speed IO_MUX SPI2 MOSI, I2C, or GPIO when using native USB Serial/JTAG.
Digital GPIO7, direct IO_MUX SPI2 MOSI (FSPID), and JTAG MTDO (3.3V max, NOT 5V tolerant)
|
| 22 | IO8 GPIO8 | digital | GPIO8 LEDC_CH2 |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — MUST be HIGH for Download Boot)
Sampled at reset with no internal pull-up. Entering Joint Download Boot (GPIO9=LOW) strictly requires GPIO8=HIGH (GPIO8=0 & GPIO9=0 is an invalid boot state!). Add an external 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Digital GPIO8 (Download Boot gate & ROM UART0 print strapping pin)
|
| 23 | IO9 GPIO9 | digital | GPIO9 LEDC_CH3 |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=Download Boot)
Sampled at reset with internal ~45 kΩ pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters Joint Download Boot (USB Serial/JTAG + UART0). Avoid external loads that pull GPIO9 low at power-on.
Digital GPIO9 (BOOT button strapping pin with internal weak pull-up)
|
| 24 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 25 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 26 | IO18 GPIO18 | special | GPIO18 USB_D- U0RTS LEDC_CH4 |
[CAUTION] Native Full-Speed USB Serial/JTAG D− differential line
Enabled by default as USB D− for flashing, CDC console, and JTAG debugging. Reconfiguring GPIO18 as digital I/O disconnects native USB until reset.
Native USB 2.0 Full-Speed Serial/JTAG D− pad / Digital GPIO18
|
| 27 | IO19 GPIO19 | special | GPIO19 USB_D+ U0CTS LEDC_CH5 |
[CAUTION] Native Full-Speed USB Serial/JTAG D+ line (internal 1.5 kΩ USB pull-up active at reset)
Enabled by default with an internal USB D+ pull-up to 3.3V at reset. Reconfiguring GPIO19 as digital I/O disconnects native USB Serial/JTAG.
Native USB 2.0 Full-Speed Serial/JTAG D+ pad / Digital GPIO19
|
| 28 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 29 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 30 | RXD0 GPIO20 | digital | GPIO20 U0RXD LEDC_CH0 |
[INFO] Default ROM bootloader UART0 RX input (internal pull-up active during boot)
Used by the ROM serial bootloader alongside USB Serial/JTAG in Download Boot mode. Freely usable for UART0 RX or general GPIO after boot.
Digital GPIO20 and default UART0 RX (U0RXD) (3.3V max, NOT 5V tolerant)
|
| 31 | TXD0 GPIO21 | digital | GPIO21 U0TXD LEDC_CH1 |
[INFO] Default ROM bootloader UART0 TX output (emits 115200 baud boot log at reset)
Outputs ROM boot diagnostic messages on reset unless suppressed by GPIO8 / EFUSE_UART_PRINT_CONTROL. Freely usable for UART0 TX or general GPIO after boot.
Digital GPIO21 and default UART0 TX (U0TXD) (3.3V max, NOT 5V tolerant)
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| 32 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 33 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 34 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 35 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 36-53 | GND | ground | GND |
Underside LGA shield-return & central 3×3 exposed thermal ground pad array (Pins 36–53, 0V)
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