Espressif's ESP32-C3 combines a 160 MHz single-core 32-bit RISC-V processor with 400 KB SRAM (including 16 KB RTC SRAM), 384 KB ROM, and external or 4 MB/8 MB in-package Quad SPI flash in a compact 5×5 mm QFN-32 footprint. Alongside 2.4 GHz Wi-Fi 4 (802.11b/g/n) and Bluetooth 5.0 LE radios, its flexible GPIO Matrix routes 2× UART, SPI2, I2C0, I2S0, TWAI (CAN), and 6× LEDC PWM channels across up to 22 GPIOs (15 available when SPI flash is active) plus native USB Serial/JTAG on GPIO18/GPIO19. Five reliable 12-bit SAR ADC1 channels span GPIO0–GPIO4 across a 3.0 V–3.6 V supply (ADC2 on GPIO5 is affected by silicon errata [ADC-183]). All I/Os are strictly 3.3 V non-5V-tolerant, and GPIO8 must remain HIGH when pulling GPIO9 LOW for Download Boot.
On ESP32-C3FH4 and ESP32-C3FN4 SiP variants, leave Pins 18–24 floating externally; on bare external-flash ESP32-C3, route Pins 18–24 to an external 3.3V Quad SPI flash IC.
Add the peripherals you need and plan the pin assignments
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | LNA_IN | special | LNA_IN |
[INFO] 2.4 GHz 50Ω RF antenna port
Dedicated 2.4 GHz RF input/output for Wi-Fi 4 and Bluetooth 5 LE. Requires an external 50Ω impedance-matching network.
2.4 GHz RF antenna input/output pin
|
| 2 | VDD3P3 | power | VDD3P3 |
Analog & PA power supply (3.0V–3.6V, 3.3V nominal)
|
| 3 | VDD3P3 | power | VDD3P3 |
Analog & PA power supply (3.0V–3.6V, 3.3V nominal)
|
| 4 | GPIO0 | mixed | GPIO0 ADC1_CH0 XTAL_32K_P LEDC_CH0 |
RTC/Digital GPIO0, 12-bit ADC1_CH0, and 32.768 kHz crystal P (3.3V max, NOT 5V tolerant)
|
| 5 | GPIO1 | mixed | GPIO1 ADC1_CH1 XTAL_32K_N LEDC_CH1 |
RTC/Digital GPIO1, 12-bit ADC1_CH1, and 32.768 kHz crystal N (3.3V max, NOT 5V tolerant)
|
| 6 | GPIO2 | mixed | GPIO2 ADC1_CH2 FSPIQ LEDC_CH2 |
[CAUTION] Boot strapping pin (must be HIGH during Download Boot)
Sampled at reset with no internal pull-up enabled. Keep GPIO2 HIGH (or add a 10 kΩ pull-up) when entering Joint Download Boot via GPIO9=LOW to prevent unintended glitch modes.
RTC/Digital GPIO2, 12-bit ADC1_CH2, direct IO_MUX SPI2 MISO (FSPIQ), and boot strapping pin
|
| 7 | CHIP_EN CHIP_PU | reset | CHIP_EN |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND) to meet power-on reset timing.
High-enable / active-low chip reset input (CHIP_EN / EN)
|
| 8 | GPIO3 | mixed | GPIO3 ADC1_CH3 LEDC_CH3 |
RTC/Digital GPIO3 and 12-bit ADC1_CH3 (3.3V max, NOT 5V tolerant)
|
| 9 | GPIO4 | mixed | GPIO4 ADC1_CH4 FSPIHD MTMS LEDC_CH4 |
[INFO] Dedicated JTAG MTMS pin if external JTAG probe is enabled
Free for ADC1_CH4, SPI2, or general GPIO when debugging over native USB Serial/JTAG (GPIO18/GPIO19).
RTC/Digital GPIO4, 12-bit ADC1_CH4, FSPIHD, and JTAG MTMS (3.3V max, NOT 5V tolerant)
|
| 10 | GPIO5 | mixed | GPIO5 ADC2_CH0 FSPIWP MTDI LEDC_CH5 |
[CAUTION] ADC2_CH0 affected by silicon errata [ADC-183] & Wi-Fi arbitration — prefer GPIO0–GPIO4 for analog
Hardware errata [ADC-183] disables continuous/DMA ADC2 operation on ESP32-C3, and ADC2 is shared with the Wi-Fi radio. Safe as a standard digital GPIO; use GPIO0–GPIO4 (ADC1) for reliable analog reads.
RTC/Digital GPIO5, ADC2_CH0 (see errata), FSPIWP, and JTAG MTDI
|
| 11 | VDD3P3_RTC | power | VDD3P3_RTC |
RTC and low-power I/O domain power supply for GPIO0–GPIO5 (3.0V–3.6V)
|
| 12 | GPIO6 | digital | GPIO6 FSPICLK MTCK LEDC_CH0 |
[INFO] Dedicated JTAG MTCK pin if external JTAG probe is enabled
Completely free for high-speed IO_MUX SPI2 SCK, I2C, or GPIO when using native USB Serial/JTAG.
Digital GPIO6, direct IO_MUX SPI2 SCK (FSPICLK), and JTAG MTCK (3.3V max, NOT 5V tolerant)
|
| 13 | GPIO7 | digital | GPIO7 FSPID MTDO LEDC_CH1 |
[INFO] Dedicated JTAG MTDO pin if external JTAG probe is enabled
Completely free for high-speed IO_MUX SPI2 MOSI, I2C, or GPIO when using native USB Serial/JTAG.
Digital GPIO7, direct IO_MUX SPI2 MOSI (FSPID), and JTAG MTDO (3.3V max, NOT 5V tolerant)
|
| 14 | GPIO8 | digital | GPIO8 LEDC_CH2 |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — MUST be HIGH for Download Boot)
Sampled at reset with no internal pull-up. Entering Joint Download Boot (GPIO9=LOW) strictly requires GPIO8=HIGH (GPIO8=0 & GPIO9=0 is an invalid boot state!). Add an external 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Digital GPIO8 (Download Boot gate & ROM UART0 print strapping pin)
|
| 15 | GPIO9 | digital | GPIO9 LEDC_CH3 |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=Download Boot)
Sampled at reset with internal ~45 kΩ pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters Joint Download Boot (USB Serial/JTAG + UART0). Avoid external loads that pull GPIO9 low at power-on.
Digital GPIO9 (BOOT button strapping pin with internal weak pull-up)
|
| 16 | GPIO10 | digital | GPIO10 FSPICS0 LEDC_CH4 |
Digital GPIO10 and direct IO_MUX SPI2 CS0 (FSPICS0) (3.3V max, NOT 5V tolerant)
|
| 17 | VDD3P3_CPU | power | VDD3P3_CPU |
Digital CPU and I/O power supply domain for GPIO6–GPIO21 (3.0V–3.6V)
|
| 18 | VDD_SPI GPIO11 | power | VDD_SPI GPIO11 |
[DANGER] 3.3V internal LDO output for SPI flash (GPIO11 only if EFUSE_VDD_SPI_AS_GPIO=1)
Powers in-package or external 3.3V Quad SPI flash by default. Must not be used as GPIO11 on FH4/FN4 chips or standard modules where VDD_SPI feeds flash.
3.3V SPI flash power supply output (VDD_SPI) / optional GPIO11
|
| 19 | SPIHD GPIO12 | digital | SPIHD GPIO12 |
[DANGER] Dedicated SPI0/1 XIP flash HOLD / IO3 — do not use for external I/O
Connected to internal/onboard Quad SPI execute-in-place (XIP) flash memory on FH4/FN4 SiPs and modules. Leave unconnected externally.
Primary SPI0/1 flash Hold / IO3 (SPIHD) / GPIO12
|
| 20 | SPIWP GPIO13 | digital | SPIWP GPIO13 |
[DANGER] Dedicated SPI0/1 XIP flash WP / IO2 — do not use for external I/O
Connected to internal/onboard Quad SPI execute-in-place (XIP) flash memory on FH4/FN4 SiPs and modules. Leave unconnected externally.
Primary SPI0/1 flash Write Protect / IO2 (SPIWP) / GPIO13
|
| 21 | SPICS0 GPIO14 | digital | SPICS0 GPIO14 |
[DANGER] Dedicated SPI0/1 XIP flash Chip Select — do not use for external I/O
Connected to internal/onboard Quad SPI execute-in-place (XIP) flash CS0. Repurposing crashes firmware execution.
Primary SPI0/1 flash Chip Select (SPICS0) / GPIO14
|
| 22 | SPICLK GPIO15 | digital | SPICLK GPIO15 |
[DANGER] Dedicated SPI0/1 XIP flash clock — do not use for external I/O
Connected to internal/onboard Quad SPI execute-in-place (XIP) flash clock (up to 80 MHz). Do not attach external loads.
Primary SPI0/1 flash clock (SPICLK) / GPIO15
|
| 23 | SPID GPIO16 | digital | SPID GPIO16 |
[DANGER] Dedicated SPI0/1 XIP flash MOSI / IO0 — do not use for external I/O
Connected to internal/onboard Quad SPI execute-in-place (XIP) flash data IO0 (SPID). Do not attach external loads.
Primary SPI0/1 flash MOSI / IO0 (SPID) / GPIO16
|
| 24 | SPIQ GPIO17 | digital | SPIQ GPIO17 |
[DANGER] Dedicated SPI0/1 XIP flash MISO / IO1 — do not use for external I/O
Connected to internal/onboard Quad SPI execute-in-place (XIP) flash data IO1 (SPIQ). Do not attach external loads.
Primary SPI0/1 flash MISO / IO1 (SPIQ) / GPIO17
|
| 25 | GPIO18 | special | GPIO18 USB_D- U0RTS LEDC_CH4 |
[CAUTION] Native Full-Speed USB Serial/JTAG D− differential line
Enabled by default as USB D− for flashing, CDC console, and JTAG debugging. Reconfiguring GPIO18 as digital I/O disconnects native USB until reset.
Native USB 2.0 Full-Speed Serial/JTAG D− pad / Digital GPIO18
|
| 26 | GPIO19 | special | GPIO19 USB_D+ U0CTS LEDC_CH5 |
[CAUTION] Native Full-Speed USB Serial/JTAG D+ line (internal 1.5 kΩ USB pull-up active at reset)
Enabled by default with an internal USB D+ pull-up to 3.3V at reset. Reconfiguring GPIO19 as digital I/O disconnects native USB Serial/JTAG.
Native USB 2.0 Full-Speed Serial/JTAG D+ pad / Digital GPIO19
|
| 27 | U0RXD GPIO20 | digital | GPIO20 U0RXD LEDC_CH0 |
[INFO] Default ROM bootloader UART0 RX input (internal pull-up active during boot)
Used by the ROM serial bootloader alongside USB Serial/JTAG in Download Boot mode. Freely usable for UART0 RX or general GPIO after boot.
Digital GPIO20 and default UART0 RX (U0RXD) (3.3V max, NOT 5V tolerant)
|
| 28 | U0TXD GPIO21 | digital | GPIO21 U0TXD LEDC_CH1 |
[INFO] Default ROM bootloader UART0 TX output (emits 115200 baud boot log at reset)
Outputs ROM boot diagnostic messages on reset unless suppressed by GPIO8 / EFUSE_UART_PRINT_CONTROL. Freely usable for UART0 TX or general GPIO after boot.
Digital GPIO21 and default UART0 TX (U0TXD) (3.3V max, NOT 5V tolerant)
|
| 29 | XTAL_N | clock | XTAL_N |
[INFO] 40 MHz RF reference crystal negative pin
Dedicated 40 MHz ±10 ppm crystal oscillator pin required for Wi-Fi and Bluetooth LE operation.
External 40 MHz crystal oscillator negative input/output
|
| 30 | XTAL_P | clock | XTAL_P |
[INFO] 40 MHz RF reference crystal positive pin
Dedicated 40 MHz ±10 ppm crystal oscillator pin required for Wi-Fi and Bluetooth LE operation.
External 40 MHz crystal oscillator positive input/output
|
| 31 | VDDA | power | VDDA |
Analog, PLL, and crystal oscillator power supply (3.0V–3.6V)
|
| 32 | VDDA | power | VDDA |
Analog, PLL, and crystal oscillator power supply (3.0V–3.6V)
|
| 33 | GND | ground | GND |
Central exposed thermal and electrical ground pad (0V)
|