Integrating Espressif's QFN-32 ESP32-C6FH4/FH8 SiP (160 MHz RISC-V HP + 20 MHz LP cores, 512 KB HP SRAM, and 4 MB or 8 MB in-package Quad SPI flash) with a 40 MHz crystal, the ESP32-C6-MINI-1 shrinks tri-radio Wi-Fi 6, Bluetooth 5.3 LE, and 802.15.4 connectivity into 13.2×16.6 mm (PCB antenna) and 13.2×12.5 mm (MINI-1U external antenna) 0.8 mm LGA footprints. Twenty-two exposed 3.3 V GPIOs (including IO14, with IO10/IO11 unbonded) support GPIO Matrix routing for UART, SPI2, I2C, I2S, TWAI, PWM, and native USB (IO12/IO13). Seven 12-bit 100 ksps SAR ADC1 inputs cover IO0–IO6 across a 3.0 V–3.6 V rail. All I/Os are strictly non-5V-tolerant, and IO8/IO9 boot strapping rules apply.
Quad SPI XIP flash is integrated inside the QFN-32 SiP package under the RF shield.
ESP32-C6-MINI-1 exposes IO14 (Pin 19) instead of IO10/IO11.
Add the peripherals you need and plan the pin assignments
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | GND | ground | GND |
Module system ground (0V)
|
| 2 | GND | ground | GND |
Module system ground (0V)
|
| 3 | 3V3 | power | 3V3 |
[CAUTION] 3.0V–3.6V supply only (>=500 mA regulator + 10 µF & 0.1 µF bypass caps near Pin 3)
Radio transmit bursts require low-impedance 3.3V power delivery. Exceeding 3.6V permanently damages the SoC.
Main 3.3V module power supply input (3.0V–3.6V; >=500 mA current capability recommended)
|
| 4 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 5 | IO2 GPIO2 | mixed | GPIO2 ADC1_CH2 FSPIQ LP_GPIO2 LP_UART_RTSN LEDC_CH2 |
General Purpose LP/HP I/O 2, 12-bit ADC1_CH2, and direct IO_MUX SPI2 MISO (FSPIQ)
|
| 6 | IO3 GPIO3 | mixed | GPIO3 ADC1_CH3 LP_GPIO3 LP_UART_CTSN LEDC_CH3 |
General Purpose LP/HP I/O 3 and 12-bit ADC1_CH3 (3.3V max, NOT 5V tolerant)
|
| 7 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 8 | EN CHIP_PU | reset | CHIP_PU |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND) for clean power-on reset timing.
Ref: ESP32-C6 Datasheet v1.6 §2.4, Table 2-12
High-enable / active-low chip reset input (EN)
|
| 9 | IO4 GPIO4 | mixed | GPIO4 ADC1_CH4 LP_UART_RXD MTMS FSPIHD LP_GPIO4 LEDC_CH4 |
[CAUTION] SDIO sampling-edge strapping pin & JTAG MTMS (floating at reset)
Sampled during CHIP_PU reset alongside GPIO5 to configure SDIO slave timing; also serves as JTAG TMS unless USB Serial/JTAG is used. Safe for general GPIO/ADC when SDIO slave boot is unused.
Ref: ESP32-C6 Datasheet v1.6 §3, Table 3-1 & §3.2, Table 3-4
General Purpose LP/HP I/O 4, 12-bit ADC1_CH4, LP_UART RX, and JTAG MTMS
|
| 10 | IO5 GPIO5 | mixed | GPIO5 ADC1_CH5 LP_UART_TXD MTDI FSPIWP LP_GPIO5 LEDC_CH5 |
[CAUTION] SDIO driving-edge strapping pin & JTAG MTDI (floating at reset)
Sampled during CHIP_PU reset alongside GPIO4 to configure SDIO slave timing; also serves as JTAG TDI unless USB Serial/JTAG is used. Safe for general GPIO/ADC when SDIO slave boot is unused.
Ref: ESP32-C6 Datasheet v1.6 §3, Table 3-1 & §3.2, Table 3-4
General Purpose LP/HP I/O 5, 12-bit ADC1_CH5, LP_UART TX, and JTAG MTDI
|
| 11 | GND | ground | GND |
Module system ground (0V)
|
| 12 | IO0 GPIO0 | mixed | GPIO0 ADC1_CH0 XTAL_32K_P LP_GPIO0 LP_UART_DTRN LEDC_CH0 |
General Purpose LP/HP I/O 0, 12-bit ADC1_CH0, and 32.768 kHz crystal P (3.3V max, NOT 5V tolerant)
|
| 13 | IO1 GPIO1 | mixed | GPIO1 ADC1_CH1 XTAL_32K_N LP_GPIO1 LP_UART_DSRN LEDC_CH1 |
General Purpose LP/HP I/O 1, 12-bit ADC1_CH1, and 32.768 kHz crystal N (3.3V max, NOT 5V tolerant)
|
| 14 | GND | ground | GND |
Module system ground (0V)
|
| 15 | IO6 GPIO6 | mixed | GPIO6 ADC1_CH6 FSPICLK LP_I2C_SDA MTCK LP_GPIO6 MCPWM0_0A |
[INFO] Dedicated JTAG MTCK pin if external JTAG probe is enabled
Defaults to JTAG TCK only when external JTAG is selected; completely free for ADC1_CH6, SPI2 SCK, I2C, or GPIO when debugging via USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.3.4 & §3.4
General Purpose LP/HP I/O 6, 12-bit ADC1_CH6, direct IO_MUX SPI2 SCK (FSPICLK), and LP_I2C SDA
|
| 16 | IO7 GPIO7 | digital | GPIO7 FSPID LP_I2C_SCL MTDO LP_GPIO7 MCPWM0_0B |
[INFO] Dedicated JTAG MTDO pin if external JTAG probe is enabled
Note that GPIO7 has NO ADC channel on ESP32-C6 (ADC1 spans GPIO0–GPIO6 only). Free for SPI2 MOSI, LP_I2C SCL, or GPIO when using USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.3.3, Table 2-9 & §3.4
General Purpose LP/HP I/O 7 (digital only — no ADC), direct IO_MUX SPI2 MOSI (FSPID), and LP_I2C SCL
|
| 17 | IO12 GPIO12 | special | GPIO12 USB_D- LEDC_CH0 |
[CAUTION] Native Full-Speed USB Serial/JTAG D− differential line
Enabled by default as USB D− for flashing, console logging, and JTAG debugging. Reconfiguring GPIO12 as digital I/O disconnects native USB until reset.
Ref: ESP32-C6 Datasheet v1.6 §2.3.3, Table 2-9 & §2.3.4
Native USB 2.0 Full-Speed Serial/JTAG D− pad / General Purpose HP I/O 12
|
| 18 | IO13 GPIO13 | special | GPIO13 USB_D+ LEDC_CH1 |
[CAUTION] Native Full-Speed USB Serial/JTAG D+ line (internal USB pull-up active at reset)
Enabled by default with an internal 1.5 kΩ USB D+ pull-up to 3.3V at reset. Reconfiguring GPIO13 as digital I/O disconnects native USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.2, Table 2-1 & §2.3.4
Native USB 2.0 Full-Speed Serial/JTAG D+ pad / General Purpose HP I/O 13
|
| 19 | IO14 GPIO14 | digital | GPIO14 LEDC_CH2 |
General Purpose HP I/O 14 (bonded on QFN32 / MINI-1; not bonded on QFN40 / WROOM-1)
|
| 20 | IO15 GPIO15 | digital | GPIO15 LEDC_CH3 |
[CAUTION] JTAG signal-source strapping pin (floating at reset when eFuse JTAG_SEL enabled)
Sampled at reset only if EFUSE_JTAG_SEL_ENABLE=1 (HIGH selects USB Serial/JTAG, LOW selects pad JTAG on GPIO4–GPIO7). Ignored by default factory eFuse configuration, making it usable as standard GPIO.
Ref: ESP32-C6 Datasheet v1.6 §3.4, Table 3-7
General Purpose HP I/O 15 (optional JTAG source selector strapping pin)
|
| 21 | NC | nc | — |
No internal connection (IO10/IO11 unbonded on QFN-32) — leave floating on host PCB
|
| 22 | IO8 GPIO8 | digital | GPIO8 MCPWM0_1A |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — must be HIGH for Download Boot)
Sampled at reset with no internal pull resistor. Entering Download Boot (GPIO9=0) requires GPIO8=1 (GPIO8=0 & GPIO9=0 is an invalid boot combination!). Also gates ROM UART0 boot messages when EFUSE_UART_PRINT_CONTROL=1/2. Add a 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Ref: ESP32-C6 Datasheet v1.6 §3.1, Table 3-3 & §3.3, Table 3-5
General Purpose HP I/O 8 (boot mode & ROM print strapping pin, 40 mA max source)
|
| 23 | IO9 GPIO9 | digital | GPIO9 MCPWM0_1B |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=Download Boot)
Sampled at reset with internal ~45 kΩ pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters Joint Download Boot (USB Serial/JTAG + UART0). Do not attach external loads that hold GPIO9 low at power-up.
Ref: ESP32-C6 Datasheet v1.6 §3.1, Table 3-3
General Purpose HP I/O 9 (BOOT button strapping pin with internal weak pull-up)
|
| 24 | IO18 GPIO18 | digital | GPIO18 SDIO_CMD FSPICS2 MCPWM0_0A |
General Purpose HP I/O 18, SDIO Slave CMD, and direct IO_MUX FSPICS2 (3.3V max, NOT 5V tolerant)
|
| 25 | IO19 GPIO19 | digital | GPIO19 SDIO_CLK FSPICS3 MCPWM0_0B |
General Purpose HP I/O 19, SDIO Slave CLK, and direct IO_MUX FSPICS3 (3.3V max, NOT 5V tolerant)
|
| 26 | IO20 GPIO20 | digital | GPIO20 SDIO_DATA0 FSPICS4 MCPWM0_1A |
General Purpose HP I/O 20, SDIO Slave DATA0, and direct IO_MUX FSPICS4 (3.3V max, NOT 5V tolerant)
|
| 27 | IO21 GPIO21 | digital | GPIO21 SDIO_DATA1 FSPICS5 MCPWM0_1B |
General Purpose HP I/O 21, SDIO Slave DATA1, and direct IO_MUX FSPICS5 (3.3V max, NOT 5V tolerant)
|
| 28 | IO22 GPIO22 | digital | GPIO22 SDIO_DATA2 MCPWM0_2A |
General Purpose HP I/O 22 and SDIO Slave DATA2 (3.3V max, NOT 5V tolerant)
|
| 29 | IO23 GPIO23 | digital | GPIO23 SDIO_DATA3 MCPWM0_2B |
General Purpose HP I/O 23 and SDIO Slave DATA3 (3.3V max, NOT 5V tolerant)
|
| 30 | RXD0 GPIO17 | digital | GPIO17 U0RXD FSPICS1 LEDC_CH5 |
[INFO] Default ROM bootloader UART0 RX input (internal pull-up active during boot)
Used by the ROM serial bootloader alongside USB Serial/JTAG in Download Boot mode. Freely usable for UART0 RX or general GPIO after boot.
Ref: ESP32-C6 Datasheet v1.6 §2.2, Table 2-1 & §2.3.1, Table 2-4
General Purpose HP I/O 17, default UART0 RX (U0RXD), and direct IO_MUX SPI2 CS1 (FSPICS1)
|
| 31 | TXD0 GPIO16 | digital | GPIO16 U0TXD FSPICS0 LEDC_CH4 |
[INFO] Default ROM bootloader UART0 TX output (toggles at 115200 baud during reset)
Outputs ROM boot log messages at power-up/reset unless muted via eFuse or GPIO8 strapping. Can be reassigned after boot via the GPIO Matrix.
Ref: ESP32-C6 Datasheet v1.6 §2.3.1, Table 2-4 & §3.3
General Purpose HP I/O 16, default UART0 TX (U0TXD), and direct IO_MUX SPI2 CS0 (FSPICS0)
|
| 32 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 33 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 34 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 35 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 36-53 | GND | ground | GND |
Underside LGA shield-return & central 3×3 exposed thermal ground pad array (Pins 36–53, 0V)
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