Espressif's ESP32-C6 pairs a 160 MHz 32-bit RISC-V high-performance core with a 20 MHz low-power RISC-V co-processor, 512 KB HP SRAM, 16 KB LP SRAM, 320 KB ROM, and a Quad SPI XIP flash interface in 5×5 mm QFN-40 (external flash) and QFN-32 (4 MB/8 MB SiP flash) packages. Alongside 2.4 GHz Wi-Fi 6 (802.11ax), Bluetooth 5.3 LE, and IEEE 802.15.4 radios, its flexible GPIO Matrix routes 2× HP UART, 1× LP UART, SPI2, HP/LP I2C, I2S, 2× TWAI (CAN), 6× LEDC, and 6× MCPWM channels across up to 30 GPIOs plus native USB Serial/JTAG. Seven 12-bit 100 ksps SAR ADC inputs occupy GPIO0–GPIO6 across a 3.0 V–3.6 V supply. All I/Os are strictly 3.3 V non-5V-tolerant, and GPIO8 must remain HIGH when pulling GPIO9 LOW for Download Boot.
QFN-40 exposes external SPI0/1 flash pads (GPIO24–GPIO30) plus GPIO10 and GPIO11, leaving silicon pad GPIO14 unbonded.
Add the peripherals you need and plan the pin assignments
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | ANT | special | ANT |
[INFO] 2.4 GHz 50Ω RF antenna port
Dedicated 2.4 GHz RF input/output for Wi-Fi 6, Bluetooth 5 LE, and 802.15.4. Requires an external 50Ω matching network.
Ref: ESP32-C6 Datasheet v1.6 §2.4, Table 2-12
2.4 GHz RF antenna input/output pin
|
| 2 | VDDA3P3 | power | VDDA3P3 |
Analog & PA power supply (3.0V–3.6V, 3.3V nominal)
|
| 3 | VDDA3P3 | power | VDDA3P3 |
Analog & PA power supply (3.0V–3.6V, 3.3V nominal)
|
| 4 | CHIP_PU | reset | CHIP_PU |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND) for clean power-on reset timing.
Ref: ESP32-C6 Datasheet v1.6 §2.4, Table 2-12
High-enable / active-low chip reset input (EN)
|
| 5 | VDDPST1 | power | VDDPST1 |
LP I/O and CPU power supply domain for GPIO0–GPIO7 (3.0V–3.6V)
|
| 6 | GPIO0 | mixed | GPIO0 ADC1_CH0 XTAL_32K_P LP_GPIO0 LP_UART_DTRN LEDC_CH0 |
General Purpose LP/HP I/O 0, 12-bit ADC1_CH0, and 32.768 kHz crystal P (3.3V max, NOT 5V tolerant)
|
| 7 | GPIO1 | mixed | GPIO1 ADC1_CH1 XTAL_32K_N LP_GPIO1 LP_UART_DSRN LEDC_CH1 |
General Purpose LP/HP I/O 1, 12-bit ADC1_CH1, and 32.768 kHz crystal N (3.3V max, NOT 5V tolerant)
|
| 8 | GPIO2 | mixed | GPIO2 ADC1_CH2 FSPIQ LP_GPIO2 LP_UART_RTSN LEDC_CH2 |
General Purpose LP/HP I/O 2, 12-bit ADC1_CH2, and direct IO_MUX SPI2 MISO (FSPIQ)
|
| 9 | GPIO3 | mixed | GPIO3 ADC1_CH3 LP_GPIO3 LP_UART_CTSN LEDC_CH3 |
General Purpose LP/HP I/O 3 and 12-bit ADC1_CH3 (3.3V max, NOT 5V tolerant)
|
| 10 | GPIO4 | mixed | GPIO4 ADC1_CH4 LP_UART_RXD MTMS FSPIHD LP_GPIO4 LEDC_CH4 |
[CAUTION] SDIO sampling-edge strapping pin & JTAG MTMS (floating at reset)
Sampled during CHIP_PU reset alongside GPIO5 to configure SDIO slave timing; also serves as JTAG TMS unless USB Serial/JTAG is used. Safe for general GPIO/ADC when SDIO slave boot is unused.
Ref: ESP32-C6 Datasheet v1.6 §3, Table 3-1 & §3.2, Table 3-4
General Purpose LP/HP I/O 4, 12-bit ADC1_CH4, LP_UART RX, and JTAG MTMS
|
| 11 | GPIO5 | mixed | GPIO5 ADC1_CH5 LP_UART_TXD MTDI FSPIWP LP_GPIO5 LEDC_CH5 |
[CAUTION] SDIO driving-edge strapping pin & JTAG MTDI (floating at reset)
Sampled during CHIP_PU reset alongside GPIO4 to configure SDIO slave timing; also serves as JTAG TDI unless USB Serial/JTAG is used. Safe for general GPIO/ADC when SDIO slave boot is unused.
Ref: ESP32-C6 Datasheet v1.6 §3, Table 3-1 & §3.2, Table 3-4
General Purpose LP/HP I/O 5, 12-bit ADC1_CH5, LP_UART TX, and JTAG MTDI
|
| 12 | GPIO6 | mixed | GPIO6 ADC1_CH6 FSPICLK LP_I2C_SDA MTCK LP_GPIO6 MCPWM0_0A |
[INFO] Dedicated JTAG MTCK pin if external JTAG probe is enabled
Defaults to JTAG TCK only when external JTAG is selected; completely free for ADC1_CH6, SPI2 SCK, I2C, or GPIO when debugging via USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.3.4 & §3.4
General Purpose LP/HP I/O 6, 12-bit ADC1_CH6, direct IO_MUX SPI2 SCK (FSPICLK), and LP_I2C SDA
|
| 13 | GPIO7 | digital | GPIO7 FSPID LP_I2C_SCL MTDO LP_GPIO7 MCPWM0_0B |
[INFO] Dedicated JTAG MTDO pin if external JTAG probe is enabled
Note that GPIO7 has NO ADC channel on ESP32-C6 (ADC1 spans GPIO0–GPIO6 only). Free for SPI2 MOSI, LP_I2C SCL, or GPIO when using USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.3.3, Table 2-9 & §3.4
General Purpose LP/HP I/O 7 (digital only — no ADC), direct IO_MUX SPI2 MOSI (FSPID), and LP_I2C SCL
|
| 14 | GPIO8 | digital | GPIO8 MCPWM0_1A |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — must be HIGH for Download Boot)
Sampled at reset with no internal pull resistor. Entering Download Boot (GPIO9=0) requires GPIO8=1 (GPIO8=0 & GPIO9=0 is an invalid boot combination!). Also gates ROM UART0 boot messages when EFUSE_UART_PRINT_CONTROL=1/2. Add a 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Ref: ESP32-C6 Datasheet v1.6 §3.1, Table 3-3 & §3.3, Table 3-5
General Purpose HP I/O 8 (boot mode & ROM print strapping pin, 40 mA max source)
|
| 15 | GPIO9 | digital | GPIO9 MCPWM0_1B |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=Download Boot)
Sampled at reset with internal ~45 kΩ pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters Joint Download Boot (USB Serial/JTAG + UART0). Do not attach external loads that hold GPIO9 low at power-up.
Ref: ESP32-C6 Datasheet v1.6 §3.1, Table 3-3
General Purpose HP I/O 9 (BOOT button strapping pin with internal weak pull-up)
|
| 16 | GPIO10 | digital | GPIO10 MCPWM0_2A |
General Purpose HP I/O 10 (bonded on QFN40 / WROOM-1; not bonded on QFN32 / MINI-1)
|
| 17 | GPIO11 | digital | GPIO11 MCPWM0_2B |
General Purpose HP I/O 11 (bonded on QFN40 / WROOM-1; not bonded on QFN32 / MINI-1)
|
| 18 | GPIO12 | special | GPIO12 USB_D- LEDC_CH0 |
[CAUTION] Native Full-Speed USB Serial/JTAG D− differential line
Enabled by default as USB D− for flashing, console logging, and JTAG debugging. Reconfiguring GPIO12 as digital I/O disconnects native USB until reset.
Ref: ESP32-C6 Datasheet v1.6 §2.3.3, Table 2-9 & §2.3.4
Native USB 2.0 Full-Speed Serial/JTAG D− pad / General Purpose HP I/O 12
|
| 19 | GPIO13 | special | GPIO13 USB_D+ LEDC_CH1 |
[CAUTION] Native Full-Speed USB Serial/JTAG D+ line (internal USB pull-up active at reset)
Enabled by default with an internal 1.5 kΩ USB D+ pull-up to 3.3V at reset. Reconfiguring GPIO13 as digital I/O disconnects native USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.2, Table 2-1 & §2.3.4
Native USB 2.0 Full-Speed Serial/JTAG D+ pad / General Purpose HP I/O 13
|
| 20 | SPICS0 GPIO24 | digital | SPICS0 GPIO24 |
[DANGER] Dedicated SPI0/1 XIP flash Chip Select 0 — do not use for external I/O
Hard-wired to the primary Quad SPI execute-in-place (XIP) flash memory on modules and FH4/FH8 SiP packages. Repurposing crashes code execution.
Ref: ESP32-C6 Datasheet v1.6 §2.6, Table 2-16
Primary SPI0/1 flash Chip Select (SPICS0) / GPIO24
|
| 21 | SPIQ GPIO25 | digital | SPIQ GPIO25 |
[DANGER] Dedicated SPI0/1 XIP flash MISO / IO1 — do not use for external I/O
Hard-wired to the primary Quad SPI execute-in-place (XIP) flash bus (SPIQ / IO1). Do not attach external loads.
Ref: ESP32-C6 Datasheet v1.6 §2.6, Table 2-16
Primary SPI0/1 flash data Q / MISO (SPIQ) / GPIO25
|
| 22 | SPIWP GPIO26 | digital | SPIWP GPIO26 |
[DANGER] Dedicated SPI0/1 XIP flash WP / IO2 — do not use for external I/O
Hard-wired to the primary Quad SPI execute-in-place (XIP) flash bus (SPIWP / IO2). Required for Quad I/O flash operation.
Ref: ESP32-C6 Datasheet v1.6 §2.6, Table 2-16
Primary SPI0/1 flash Write Protect / IO2 (SPIWP) / GPIO26
|
| 23 | VDD_SPI | power | VDD_SPI GPIO27 |
[DANGER] 3.3V internal LDO output for SPI flash (GPIO27 only if disabled)
Powers external or in-package 3.3V SPI flash by default. Reconfigurable as GPIO27 only when flash is powered from an external rail and the internal VDD_SPI LDO is disabled.
Ref: ESP32-C6 Datasheet v1.6 §2.3.4 & §2.5.1, Table 2-13
3.3V SPI flash power output / optional GPIO27
|
| 24 | SPIHD GPIO28 | digital | SPIHD GPIO28 |
[DANGER] Dedicated SPI0/1 XIP flash HOLD / IO3 — do not use for external I/O
Hard-wired to the primary Quad SPI execute-in-place (XIP) flash bus (SPIHD / IO3). Required for Quad I/O flash operation.
Ref: ESP32-C6 Datasheet v1.6 §2.6, Table 2-16
Primary SPI0/1 flash Hold / IO3 (SPIHD) / GPIO28
|
| 25 | SPICLK GPIO29 | digital | SPICLK GPIO29 |
[DANGER] Dedicated SPI0/1 XIP flash clock — do not use for external I/O
Hard-wired to the primary Quad SPI execute-in-place (XIP) flash clock (SPICLK up to 80 MHz). Do not attach external loads.
Ref: ESP32-C6 Datasheet v1.6 §2.6, Table 2-16
Primary SPI0/1 flash clock (SPICLK) / GPIO29
|
| 26 | SPID GPIO30 | digital | SPID GPIO30 |
[DANGER] Dedicated SPI0/1 XIP flash MOSI / IO0 — do not use for external I/O
Hard-wired to the primary Quad SPI execute-in-place (XIP) flash bus (SPID / IO0). Do not attach external loads.
Ref: ESP32-C6 Datasheet v1.6 §2.6, Table 2-16
Primary SPI0/1 flash data D / MOSI (SPID) / GPIO30
|
| 27 | GPIO15 | digital | GPIO15 LEDC_CH3 |
[CAUTION] JTAG signal-source strapping pin (floating at reset when eFuse JTAG_SEL enabled)
Sampled at reset only if EFUSE_JTAG_SEL_ENABLE=1 (HIGH selects USB Serial/JTAG, LOW selects pad JTAG on GPIO4–GPIO7). Ignored by default factory eFuse configuration, making it usable as standard GPIO.
Ref: ESP32-C6 Datasheet v1.6 §3.4, Table 3-7
General Purpose HP I/O 15 (optional JTAG source selector strapping pin)
|
| 28 | VDDPST2 | power | VDDPST2 |
HP I/O power supply domain for GPIO8–GPIO30 (3.0V–3.6V)
|
| 29 | GPIO16 | digital | GPIO16 U0TXD FSPICS0 LEDC_CH4 |
[INFO] Default ROM bootloader UART0 TX output (toggles at 115200 baud during reset)
Outputs ROM boot log messages at power-up/reset unless muted via eFuse or GPIO8 strapping. Can be reassigned after boot via the GPIO Matrix.
Ref: ESP32-C6 Datasheet v1.6 §2.3.1, Table 2-4 & §3.3
General Purpose HP I/O 16, default UART0 TX (U0TXD), and direct IO_MUX SPI2 CS0 (FSPICS0)
|
| 30 | GPIO17 | digital | GPIO17 U0RXD FSPICS1 LEDC_CH5 |
[INFO] Default ROM bootloader UART0 RX input (internal pull-up active during boot)
Used by the ROM serial bootloader alongside USB Serial/JTAG in Download Boot mode. Freely usable for UART0 RX or general GPIO after boot.
Ref: ESP32-C6 Datasheet v1.6 §2.2, Table 2-1 & §2.3.1, Table 2-4
General Purpose HP I/O 17, default UART0 RX (U0RXD), and direct IO_MUX SPI2 CS1 (FSPICS1)
|
| 31 | GPIO18 | digital | GPIO18 SDIO_CMD FSPICS2 MCPWM0_0A |
General Purpose HP I/O 18, SDIO Slave CMD, and direct IO_MUX FSPICS2 (3.3V max, NOT 5V tolerant)
|
| 32 | GPIO19 | digital | GPIO19 SDIO_CLK FSPICS3 MCPWM0_0B |
General Purpose HP I/O 19, SDIO Slave CLK, and direct IO_MUX FSPICS3 (3.3V max, NOT 5V tolerant)
|
| 33 | GPIO20 | digital | GPIO20 SDIO_DATA0 FSPICS4 MCPWM0_1A |
General Purpose HP I/O 20, SDIO Slave DATA0, and direct IO_MUX FSPICS4 (3.3V max, NOT 5V tolerant)
|
| 34 | GPIO21 | digital | GPIO21 SDIO_DATA1 FSPICS5 MCPWM0_1B |
General Purpose HP I/O 21, SDIO Slave DATA1, and direct IO_MUX FSPICS5 (3.3V max, NOT 5V tolerant)
|
| 35 | GPIO22 | digital | GPIO22 SDIO_DATA2 MCPWM0_2A |
General Purpose HP I/O 22 and SDIO Slave DATA2 (3.3V max, NOT 5V tolerant)
|
| 36 | GPIO23 | digital | GPIO23 SDIO_DATA3 MCPWM0_2B |
General Purpose HP I/O 23 and SDIO Slave DATA3 (3.3V max, NOT 5V tolerant)
|
| 37 | VDDA1 | power | VDDA1 |
Analog & PLL power supply 1 (3.0V–3.6V)
|
| 38 | XTAL_N | clock | XTAL_N |
[INFO] 40 MHz RF reference crystal negative pin
Dedicated 40 MHz ±10 ppm crystal oscillator pin required for Wi-Fi, Bluetooth LE, and 802.15.4 radio operation.
Ref: ESP32-C6 Datasheet v1.6 §2.4, Table 2-12
External 40 MHz crystal oscillator negative input/output
|
| 39 | XTAL_P | clock | XTAL_P |
[INFO] 40 MHz RF reference crystal positive pin
Dedicated 40 MHz ±10 ppm crystal oscillator pin required for Wi-Fi, Bluetooth LE, and 802.15.4 radio operation.
Ref: ESP32-C6 Datasheet v1.6 §2.4, Table 2-12
External 40 MHz crystal oscillator positive input/output
|
| 40 | VDDA2 | power | VDDA2 |
Analog & crystal oscillator power supply 2 (3.0V–3.6V)
|
| 41 | GND | ground | GND |
Central exposed thermal and electrical ground pad (0V)
|