Integrating Espressif's 120 MHz 32-bit RISC-V ESP8684H2/H4 (ESP32-C2) SiP, 2 MB or 4 MB of stacked Quad SPI flash, and a 26 MHz crystal, the ESP8684-MINI-1 packs 2.4 GHz Wi-Fi 4 and Bluetooth 5 LE into 13.2×16.6 mm (PCB antenna) and 13.2×12.5 mm (MINI-1U external antenna) 53-pad 0.8 mm LGA footprints compatible with Espressif's MINI-1 series. Fourteen exposed 3.3 V GPIOs (IO0–IO10, IO18, RXD0/IO19, TXD0/IO20) support GPIO Matrix routing for 2× UART, SPI2, I2C0, and 6× LEDC PWM channels (no native USB). Five 12-bit SAR ADC1 inputs cover IO0–IO4 across a 3.0 V–3.6 V supply. All pads are strictly non-5V-tolerant, and IO8/IO9 strapping rules apply.
Quad SPI XIP flash is integrated inside the QFN-24 SiP package under the RF shield.
Ensure firmware configures 26 MHz XTAL frequency.
MINI-1U uses the compact W.FL / MHF III coaxial footprint rather than full-size U.FL / MHF I.
Add the peripherals you need and plan the pin assignments
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | GND | ground | GND |
Module system ground (0V)
|
| 2 | GND | ground | GND |
Module system ground (0V)
|
| 3 | 3V3 | power | 3V3 |
[CAUTION] 3.0V–3.6V supply only (>=500 mA regulator + 10 µF & 0.1 µF bypass caps near Pin 3)
Wi-Fi transmit bursts require low-impedance 3.3V power delivery. Exceeding 3.6V permanently damages the SoC.
Main 3.3V module power supply input (3.0V–3.6V; >=500 mA current capability recommended)
|
| 4 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 5 | IO2 GPIO2 | mixed | GPIO2 ADC1_CH2 FSPIQ LEDC_CH2 |
RTC/Digital GPIO2, 12-bit ADC1_CH2, and direct IO_MUX SPI2 MISO (FSPIQ) (3.3V max, NOT 5V tolerant)
|
| 6 | IO3 GPIO3 | mixed | GPIO3 ADC1_CH3 LEDC_CH3 |
[INFO] Brief low-level glitch possible during power-up reset
May experience a brief low-level pulse during initial power-on before I/O mux latches stabilize.
RTC/Digital GPIO3 and 12-bit ADC1_CH3 (3.3V max, NOT 5V tolerant)
|
| 7 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 8 | EN CHIP_PU | reset | CHIP_EN |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND) for clean power-on reset timing.
High-enable / active-low chip reset input (CHIP_EN / EN)
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| 9 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 10 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 11 | GND | ground | GND |
Module system ground (0V)
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| 12 | IO0 GPIO0 | mixed | GPIO0 ADC1_CH0 XTAL_32K_P LEDC_CH0 |
[INFO] Brief low-level glitch possible during power-up reset
May experience a brief low-level pulse during initial power-on before I/O mux latches stabilize.
RTC/Digital GPIO0, 12-bit ADC1_CH0, and optional 32.768 kHz crystal P (3.3V max, NOT 5V tolerant)
|
| 13 | IO1 GPIO1 | mixed | GPIO1 ADC1_CH1 XTAL_32K_N LEDC_CH1 |
[INFO] Brief low-level glitch possible during power-up reset
May experience a brief low-level pulse during initial power-on before I/O mux latches stabilize.
RTC/Digital GPIO1, 12-bit ADC1_CH1, and optional 32.768 kHz crystal N (3.3V max, NOT 5V tolerant)
|
| 14 | GND | ground | GND |
Module system ground (0V)
|
| 15 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 16 | IO10 GPIO10 | digital | GPIO10 FSPICS0 LEDC_CH4 |
Digital GPIO10 and direct IO_MUX SPI2 CS0 (FSPICS0) (3.3V max, NOT 5V tolerant)
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| 17 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 18 | IO4 GPIO4 | mixed | GPIO4 ADC1_CH4 FSPIHD MTMS LEDC_CH4 |
[INFO] Dedicated JTAG MTMS pin (no native USB JTAG on ESP32-C2)
Used as JTAG TMS when debugging via external JTAG probe; freely usable for ADC1_CH4 or GPIO otherwise.
RTC/Digital GPIO4, 12-bit ADC1_CH4, FSPIHD, and JTAG MTMS (3.3V max, NOT 5V tolerant)
|
| 19 | IO5 GPIO5 | digital | GPIO5 FSPIWP MTDI LEDC_CH5 |
[INFO] Dedicated JTAG MTDI pin & brief power-up low glitch
Digital-only on ESP32-C2 (ADC1 spans GPIO0–GPIO4 only). Used for JTAG TDI if hardware JTAG is active.
RTC/Digital GPIO5 (digital only — no ADC on ESP32-C2), FSPIWP, and JTAG MTDI
|
| 20 | IO6 GPIO6 | digital | GPIO6 FSPICLK MTCK LEDC_CH0 |
[INFO] Dedicated JTAG MTCK pin when hardware JTAG debugging is used
Freely usable for direct IO_MUX SPI2 SCK (FSPICLK), I2C, or GPIO when JTAG is unused.
Digital GPIO6, direct IO_MUX SPI2 SCK (FSPICLK), and JTAG MTCK (3.3V max, NOT 5V tolerant)
|
| 21 | IO7 GPIO7 | digital | GPIO7 FSPID MTDO LEDC_CH1 |
[INFO] Dedicated JTAG MTDO pin when hardware JTAG debugging is used
Freely usable for direct IO_MUX SPI2 MOSI (FSPID), I2C, or GPIO when JTAG is unused.
Digital GPIO7, direct IO_MUX SPI2 MOSI (FSPID), and JTAG MTDO (3.3V max, NOT 5V tolerant)
|
| 22 | IO8 GPIO8 | digital | GPIO8 LEDC_CH2 |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — MUST be HIGH for Download Boot)
Sampled at reset with no internal pull-up. Entering UART0 Download Boot (GPIO9=LOW) strictly requires GPIO8=HIGH (GPIO8=0 & GPIO9=0 is an invalid boot state!). Add a 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Digital GPIO8 (Download Boot gate & ROM UART0 print strapping pin)
|
| 23 | IO9 GPIO9 | digital | GPIO9 LEDC_CH3 |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=UART0 Download Boot)
Sampled at reset with internal weak pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters UART0 Download Boot (ESP32-C2 has no native USB). Avoid external loads holding GPIO9 low at power-up.
Digital GPIO9 (BOOT button strapping pin with internal weak pull-up)
|
| 24 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 25 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 26 | IO18 GPIO18 | digital | GPIO18 LEDC_CH5 |
Digital GPIO18 (general-purpose I/O — note ESP32-C2 has no native USB peripheral)
|
| 27 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 28 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 29 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 30 | RXD0 GPIO19 | digital | GPIO19 U0RXD LEDC_CH0 |
[INFO] Primary UART0 RX input for ROM firmware flashing & console
Because ESP32-C2 omits native USB, UART0 (GPIO19 RX / GPIO20 TX) is the sole serial firmware download interface.
Digital GPIO19 and default UART0 RX (U0RXD) (3.3V max, NOT 5V tolerant)
|
| 31 | TXD0 GPIO20 | digital | GPIO20 U0TXD LEDC_CH1 |
[INFO] Primary UART0 TX output for ROM firmware flashing & boot log
Emits ROM boot log messages at reset unless suppressed via GPIO8. Serves as the sole serial flashing TX line.
Digital GPIO20 and default UART0 TX (U0TXD) (3.3V max, NOT 5V tolerant)
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| 32 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 33 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 34 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 35 | NC | nc | — |
No internal connection — leave floating on host PCB
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| 36-53 | GND | ground | GND |
Underside LGA shield-return & central 3×3 exposed thermal ground pad array (Pins 36–53, 0V)
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