ESP32-C6-WROOM-1

module
Espressif Systems Datasheet ↗

Built around Espressif's 160 MHz 32-bit RISC-V ESP32-C6 SoC (QFN-40), 40 MHz crystal, and 4 MB, 8 MB, or 16 MB of integrated Quad SPI XIP flash, the ESP32-C6-WROOM-1 comes in 18×25.5 mm PCB-antenna and 18×19.2 mm U.FL (WROOM-1U) castellated SMD footprints. Twenty-three exposed 3.3 V GPIOs (IO0–IO13, IO15–IO23) support GPIO Matrix routing for 2× HP UART, LP UART, SPI2, HP/LP I2C, I2S, 2× TWAI (CAN), LEDC/MCPWM PWM, and native USB Serial/JTAG on IO12/IO13. Seven 12-bit 100 ksps SAR ADC1 channels span IO0–IO6 across a 3.0 V–3.6 V supply (>500 mA recommended). All pads are strictly non-5V-tolerant, IO14 is unbonded, and IO8 must not be pulled low when IO9 enters Download Boot.

Silicon IC: ESP32-C6 Boards / Modules: ESP32-C6-MINI-1 Seeed Studio XIAO ESP32-C6 Also known as: ESP32-C6-WROOM-1U ESP32-C6-WROOM-1-N4 ESP32-C6-WROOM-1-N8 ESP32-C6-WROOM-1-N16
ESPRESSIF C6-WROOM-1U 1 GND GND GND 2 3V3 ! 3V3 3V3 3 EN ! CHIP_PU CHIP_PU 4 IO4 ! GPIO4 ADC1_CH4 UART Debug SPI System PWM +5 GPIO4 ADC1_CH4 LP_UART_RXD MTMS FSPIHD LP_GPIO4 LEDC_CH4 5 IO5 ! GPIO5 ADC1_CH5 UART Debug SPI System PWM +5 GPIO5 ADC1_CH5 LP_UART_TXD MTDI FSPIWP LP_GPIO5 LEDC_CH5 6 IO6 ! GPIO6 ADC1_CH6 SPI I2C Debug System PWM +5 GPIO6 ADC1_CH6 FSPICLK LP_I2C_SDA MTCK LP_GPIO6 MCPWM0_0A 7 IO7 ! GPIO7 SPI I2C Debug System PWM +5 GPIO7 FSPID LP_I2C_SCL MTDO LP_GPIO7 MCPWM0_0B 8 IO0 GPIO0 ADC1_CH0 Clock System UART PWM +4 GPIO0 ADC1_CH0 XTAL_32K_P LP_GPIO0 LP_UART_DTRN LEDC_CH0 9 IO1 GPIO1 ADC1_CH1 Clock System UART PWM +4 GPIO1 ADC1_CH1 XTAL_32K_N LP_GPIO1 LP_UART_DSRN LEDC_CH1 10 IO8 ! GPIO8 MCPWM0_1A GPIO8 MCPWM0_1A 11 IO10 GPIO10 MCPWM0_2A GPIO10 MCPWM0_2A 12 IO11 GPIO11 MCPWM0_2B GPIO11 MCPWM0_2B 13 IO12 ! GPIO12 USB_D- LEDC_CH0 GPIO12 USB_D- LEDC_CH0 14 IO13 ! GPIO13 USB_D+ LEDC_CH1 GPIO13 USB_D+ LEDC_CH1 15 IO9 ! GPIO9 MCPWM0_1B GPIO9 MCPWM0_1B 16 IO18 GPIO18 System SPI PWM +3 GPIO18 SDIO_CMD FSPICS2 MCPWM0_0A 17 IO19 GPIO19 System SPI PWM +3 GPIO19 SDIO_CLK FSPICS3 MCPWM0_0B 18 IO20 GPIO20 System SPI PWM +3 GPIO20 SDIO_DATA0 FSPICS4 MCPWM0_1A 19 IO21 GPIO21 System SPI PWM +3 GPIO21 SDIO_DATA1 FSPICS5 MCPWM0_1B 20 IO22 GPIO22 SDIO_DATA2 MCPWM0_2A GPIO22 SDIO_DATA2 MCPWM0_2A 21 IO23 GPIO23 SDIO_DATA3 MCPWM0_2B GPIO23 SDIO_DATA3 MCPWM0_2B 22 NC 23 IO15 ! GPIO15 LEDC_CH3 GPIO15 LEDC_CH3 24 RXD0 ! GPIO17 U0RXD SPI PWM +2 GPIO17 U0RXD FSPICS1 LEDC_CH5 25 TXD0 ! GPIO16 U0TXD SPI PWM +2 GPIO16 U0TXD FSPICS0 LEDC_CH4 26 IO3 GPIO3 ADC1_CH3 System UART PWM +3 GPIO3 ADC1_CH3 LP_GPIO3 LP_UART_CTSN LEDC_CH3 27 IO2 GPIO2 ADC1_CH2 SPI System UART PWM +4 GPIO2 ADC1_CH2 FSPIQ LP_GPIO2 LP_UART_RTSN LEDC_CH2 28 GND GND GND 29 EPAD GND GND

Onboard Peripherals & Internal Signals

Internal Quad SPI Flash (4 / 8 / 16 MB) QSPI
Chip Pad: GPIO24
Inside RF shield on VDD_SPI and GPIO24–GPIO30 (SPICS0, SPIQ, SPIWP, SPIHD, SPICLK, SPID)

Integrated 3.3V Quad SPI XIP flash memory inside the module shield can; flash bus pins are not routed to module perimeter pads.

40 MHz RF Crystal Oscillator Clock
Chip Pad: XTAL_P
Precision 40 MHz ±10 ppm crystal inside RF shield (XTAL_P / XTAL_N)

Provides the reference clock for Wi-Fi 6, BLE 5.3, and 802.15.4 transceivers.

External 50Ω U.FL / IPEX Antenna Connector System
Chip Pad: ANT
Top-right coaxial receptacle (connect certified 2.4 GHz external antenna before transmitting)

Replaces the 6.0 mm PCB antenna overhang of WROOM-1 for metal enclosures or high-gain external antennas.

Pin Assignment Planner

Add the peripherals you need and plan the pin assignments

Full Pin Reference (29 Pins)

Pin # Label Type Functions Warnings & Notes
1 GND ground GND
Module system ground (0V)
2 3V3 power 3V3
[CAUTION] 3.0V–3.6V supply only (provide >=500 mA current capability & local 10 µF + 0.1 µF decoupling)
Radio TX bursts require clean 3.3V regulation capable of at least 500 mA. Exceeding 3.6V permanently damages the ESP32-C6 and onboard SPI flash.
Ref: ESP32-C6-WROOM-1 Datasheet v1.4 §6.2, Table 6-2
Main 3.3V module power supply input (3.0V–3.6V; >=500 mA peak output capability recommended)
3 EN CHIP_PU reset CHIP_PU
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND) for clean power-on reset timing.
Ref: ESP32-C6 Datasheet v1.6 §2.4, Table 2-12
High-enable / active-low chip reset input (EN)
4 IO4 GPIO4 mixed GPIO4 ADC1_CH4 LP_UART_RXD MTMS FSPIHD LP_GPIO4 LEDC_CH4
[CAUTION] SDIO sampling-edge strapping pin & JTAG MTMS (floating at reset)
Sampled during CHIP_PU reset alongside GPIO5 to configure SDIO slave timing; also serves as JTAG TMS unless USB Serial/JTAG is used. Safe for general GPIO/ADC when SDIO slave boot is unused.
Ref: ESP32-C6 Datasheet v1.6 §3, Table 3-1 & §3.2, Table 3-4
General Purpose LP/HP I/O 4, 12-bit ADC1_CH4, LP_UART RX, and JTAG MTMS
5 IO5 GPIO5 mixed GPIO5 ADC1_CH5 LP_UART_TXD MTDI FSPIWP LP_GPIO5 LEDC_CH5
[CAUTION] SDIO driving-edge strapping pin & JTAG MTDI (floating at reset)
Sampled during CHIP_PU reset alongside GPIO4 to configure SDIO slave timing; also serves as JTAG TDI unless USB Serial/JTAG is used. Safe for general GPIO/ADC when SDIO slave boot is unused.
Ref: ESP32-C6 Datasheet v1.6 §3, Table 3-1 & §3.2, Table 3-4
General Purpose LP/HP I/O 5, 12-bit ADC1_CH5, LP_UART TX, and JTAG MTDI
6 IO6 GPIO6 mixed GPIO6 ADC1_CH6 FSPICLK LP_I2C_SDA MTCK LP_GPIO6 MCPWM0_0A
[INFO] Dedicated JTAG MTCK pin if external JTAG probe is enabled
Defaults to JTAG TCK only when external JTAG is selected; completely free for ADC1_CH6, SPI2 SCK, I2C, or GPIO when debugging via USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.3.4 & §3.4
General Purpose LP/HP I/O 6, 12-bit ADC1_CH6, direct IO_MUX SPI2 SCK (FSPICLK), and LP_I2C SDA
7 IO7 GPIO7 digital GPIO7 FSPID LP_I2C_SCL MTDO LP_GPIO7 MCPWM0_0B
[INFO] Dedicated JTAG MTDO pin if external JTAG probe is enabled
Note that GPIO7 has NO ADC channel on ESP32-C6 (ADC1 spans GPIO0–GPIO6 only). Free for SPI2 MOSI, LP_I2C SCL, or GPIO when using USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.3.3, Table 2-9 & §3.4
General Purpose LP/HP I/O 7 (digital only — no ADC), direct IO_MUX SPI2 MOSI (FSPID), and LP_I2C SCL
8 IO0 GPIO0 mixed GPIO0 ADC1_CH0 XTAL_32K_P LP_GPIO0 LP_UART_DTRN LEDC_CH0
General Purpose LP/HP I/O 0, 12-bit ADC1_CH0, and 32.768 kHz crystal P (3.3V max, NOT 5V tolerant)
9 IO1 GPIO1 mixed GPIO1 ADC1_CH1 XTAL_32K_N LP_GPIO1 LP_UART_DSRN LEDC_CH1
General Purpose LP/HP I/O 1, 12-bit ADC1_CH1, and 32.768 kHz crystal N (3.3V max, NOT 5V tolerant)
10 IO8 GPIO8 digital GPIO8 MCPWM0_1A
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — must be HIGH for Download Boot)
Sampled at reset with no internal pull resistor. Entering Download Boot (GPIO9=0) requires GPIO8=1 (GPIO8=0 & GPIO9=0 is an invalid boot combination!). Also gates ROM UART0 boot messages when EFUSE_UART_PRINT_CONTROL=1/2. Add a 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Ref: ESP32-C6 Datasheet v1.6 §3.1, Table 3-3 & §3.3, Table 3-5
General Purpose HP I/O 8 (boot mode & ROM print strapping pin, 40 mA max source)
11 IO10 GPIO10 digital GPIO10 MCPWM0_2A
General Purpose HP I/O 10 (bonded on QFN40 / WROOM-1; not bonded on QFN32 / MINI-1)
12 IO11 GPIO11 digital GPIO11 MCPWM0_2B
General Purpose HP I/O 11 (bonded on QFN40 / WROOM-1; not bonded on QFN32 / MINI-1)
13 IO12 GPIO12 special GPIO12 USB_D- LEDC_CH0
[CAUTION] Native Full-Speed USB Serial/JTAG D− differential line
Enabled by default as USB D− for flashing, console logging, and JTAG debugging. Reconfiguring GPIO12 as digital I/O disconnects native USB until reset.
Ref: ESP32-C6 Datasheet v1.6 §2.3.3, Table 2-9 & §2.3.4
Native USB 2.0 Full-Speed Serial/JTAG D− pad / General Purpose HP I/O 12
14 IO13 GPIO13 special GPIO13 USB_D+ LEDC_CH1
[CAUTION] Native Full-Speed USB Serial/JTAG D+ line (internal USB pull-up active at reset)
Enabled by default with an internal 1.5 kΩ USB D+ pull-up to 3.3V at reset. Reconfiguring GPIO13 as digital I/O disconnects native USB Serial/JTAG.
Ref: ESP32-C6 Datasheet v1.6 §2.2, Table 2-1 & §2.3.4
Native USB 2.0 Full-Speed Serial/JTAG D+ pad / General Purpose HP I/O 13
15 IO9 GPIO9 digital GPIO9 MCPWM0_1B
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=Download Boot)
Sampled at reset with internal ~45 kΩ pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters Joint Download Boot (USB Serial/JTAG + UART0). Do not attach external loads that hold GPIO9 low at power-up.
Ref: ESP32-C6 Datasheet v1.6 §3.1, Table 3-3
General Purpose HP I/O 9 (BOOT button strapping pin with internal weak pull-up)
16 IO18 GPIO18 digital GPIO18 SDIO_CMD FSPICS2 MCPWM0_0A
General Purpose HP I/O 18, SDIO Slave CMD, and direct IO_MUX FSPICS2 (3.3V max, NOT 5V tolerant)
17 IO19 GPIO19 digital GPIO19 SDIO_CLK FSPICS3 MCPWM0_0B
General Purpose HP I/O 19, SDIO Slave CLK, and direct IO_MUX FSPICS3 (3.3V max, NOT 5V tolerant)
18 IO20 GPIO20 digital GPIO20 SDIO_DATA0 FSPICS4 MCPWM0_1A
General Purpose HP I/O 20, SDIO Slave DATA0, and direct IO_MUX FSPICS4 (3.3V max, NOT 5V tolerant)
19 IO21 GPIO21 digital GPIO21 SDIO_DATA1 FSPICS5 MCPWM0_1B
General Purpose HP I/O 21, SDIO Slave DATA1, and direct IO_MUX FSPICS5 (3.3V max, NOT 5V tolerant)
20 IO22 GPIO22 digital GPIO22 SDIO_DATA2 MCPWM0_2A
General Purpose HP I/O 22 and SDIO Slave DATA2 (3.3V max, NOT 5V tolerant)
21 IO23 GPIO23 digital GPIO23 SDIO_DATA3 MCPWM0_2B
General Purpose HP I/O 23 and SDIO Slave DATA3 (3.3V max, NOT 5V tolerant)
22 NC nc —
No internal connection (IO14 unbonded on QFN-40) — leave floating on host PCB
23 IO15 GPIO15 digital GPIO15 LEDC_CH3
[CAUTION] JTAG signal-source strapping pin (floating at reset when eFuse JTAG_SEL enabled)
Sampled at reset only if EFUSE_JTAG_SEL_ENABLE=1 (HIGH selects USB Serial/JTAG, LOW selects pad JTAG on GPIO4–GPIO7). Ignored by default factory eFuse configuration, making it usable as standard GPIO.
Ref: ESP32-C6 Datasheet v1.6 §3.4, Table 3-7
General Purpose HP I/O 15 (optional JTAG source selector strapping pin)
24 RXD0 GPIO17 digital GPIO17 U0RXD FSPICS1 LEDC_CH5
[INFO] Default ROM bootloader UART0 RX input (internal pull-up active during boot)
Used by the ROM serial bootloader alongside USB Serial/JTAG in Download Boot mode. Freely usable for UART0 RX or general GPIO after boot.
Ref: ESP32-C6 Datasheet v1.6 §2.2, Table 2-1 & §2.3.1, Table 2-4
General Purpose HP I/O 17, default UART0 RX (U0RXD), and direct IO_MUX SPI2 CS1 (FSPICS1)
25 TXD0 GPIO16 digital GPIO16 U0TXD FSPICS0 LEDC_CH4
[INFO] Default ROM bootloader UART0 TX output (toggles at 115200 baud during reset)
Outputs ROM boot log messages at power-up/reset unless muted via eFuse or GPIO8 strapping. Can be reassigned after boot via the GPIO Matrix.
Ref: ESP32-C6 Datasheet v1.6 §2.3.1, Table 2-4 & §3.3
General Purpose HP I/O 16, default UART0 TX (U0TXD), and direct IO_MUX SPI2 CS0 (FSPICS0)
26 IO3 GPIO3 mixed GPIO3 ADC1_CH3 LP_GPIO3 LP_UART_CTSN LEDC_CH3
General Purpose LP/HP I/O 3 and 12-bit ADC1_CH3 (3.3V max, NOT 5V tolerant)
27 IO2 GPIO2 mixed GPIO2 ADC1_CH2 FSPIQ LP_GPIO2 LP_UART_RTSN LEDC_CH2
General Purpose LP/HP I/O 2, 12-bit ADC1_CH2, and direct IO_MUX SPI2 MISO (FSPIQ)
28 GND ground GND
Module system ground (0V)
29 EPAD ground GND
Underside 3×3 exposed thermal & RF ground pad (connect to host ground plane via thermal vias; optional if thermally unconstrained)