Integrating Espressif's 96 MHz 32-bit RISC-V ESP32-H2FH2/FH4 SiP (320 KB SRAM and 2 MB or 4 MB stacked Quad SPI flash) with a 32 MHz crystal, the ESP32-H2-MINI-1 delivers low-power Bluetooth 5.3 LE and IEEE 802.15.4 (Thread, Zigbee, Matter — no Wi-Fi) connectivity in 13.2×16.6 mm (PCB antenna) and 13.2×12.5 mm (MINI-1U external antenna) 53-pad 0.8 mm LGA footprints. All 19 bonded 3.3 V GPIOs (IO0–IO5, IO8–IO14, IO22–IO27) plus VBAT are exposed, supporting 2× UART, SPI2, 2× I2C, I2S0, TWAI (CAN), LEDC, MCPWM, and native USB Serial/JTAG on IO26/IO27. Five 12-bit SAR ADC1 channels cover IO1–IO5 across a 3.0 V–3.6 V rail. All I/Os are strictly non-5V-tolerant, and IO8/IO9/IO25 strapping rules apply.
Quad SPI XIP flash is integrated inside the QFN-32 SiP package under the RF shield.
Drives BLE 5.3 and IEEE 802.15.4 transceivers (no Wi-Fi radio on ESP32-H2).
Add the peripherals you need and plan the pin assignments
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | GND | ground | GND |
Module system ground (0V)
|
| 2 | GND | ground | GND |
Module system ground (0V)
|
| 3 | 3V3 | power | 3V3 |
[CAUTION] 3.0V–3.6V supply only (decouple with 10 µF & 0.1 µF near Pin 3)
Exceeding 3.6V permanently damages the ESP32-H2 silicon.
Main 3.3V module power supply input (3.0V–3.6V; >=350 mA current capability recommended)
|
| 4 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 5 | IO2 GPIO2 | mixed | GPIO2 ADC1_CH1 FSPIWP MTMS LEDC_CH2 |
[INFO] Dedicated JTAG MTMS pin if external JTAG source is selected via GPIO25
Free for ADC1_CH1, SPI2, or GPIO when debugging via native USB Serial/JTAG (GPIO26/GPIO27).
Digital/Analog GPIO2, 12-bit ADC1_CH1, FSPIWP, and JTAG MTMS
|
| 6 | IO3 GPIO3 | mixed | GPIO3 ADC1_CH2 FSPIHD MTDO LEDC_CH3 |
[INFO] Dedicated JTAG MTDO pin if external JTAG source is selected via GPIO25
Free for ADC1_CH2, SPI2, or GPIO when debugging via native USB Serial/JTAG.
Digital/Analog GPIO3, 12-bit ADC1_CH2, FSPIHD, and JTAG MTDO
|
| 7 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 8 | EN CHIP_PU | reset | CHIP_EN |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND).
High-enable / active-low chip reset input (CHIP_EN / EN)
|
| 9 | IO0 GPIO0 | digital | GPIO0 FSPIQ LEDC_CH0 |
Digital GPIO0 (no ADC on ESP32-H2 — ADC1 starts at GPIO1) and direct IO_MUX SPI2 MISO (FSPIQ)
|
| 10 | IO1 GPIO1 | mixed | GPIO1 ADC1_CH0 FSPICS0 LEDC_CH1 |
Digital/Analog GPIO1, 12-bit ADC1_CH0, and direct IO_MUX SPI2 CS0 (FSPICS0) (3.3V max, NOT 5V tolerant)
|
| 11 | GND | ground | GND |
Module system ground (0V)
|
| 12 | IO13 GPIO13 | digital | GPIO13 XTAL_32K_P LP_GPIO13 MCPWM0_2B |
Deep-sleep wakeable LP GPIO13 (VBAT domain) and optional 32.768 kHz RTC crystal P
|
| 13 | IO14 GPIO14 | digital | GPIO14 XTAL_32K_N LP_GPIO14 LEDC_CH0 |
Deep-sleep wakeable LP GPIO14 (VBAT domain) and optional 32.768 kHz RTC crystal N
|
| 14 | GND | ground | GND |
Module system ground (0V)
|
| 15 | VBAT | power | VBAT |
Battery / LP & RTC domain power supply (3.0V–3.6V; tie to 3V3 if coin-cell backup is unused)
|
| 16 | IO12 GPIO12 | digital | GPIO12 LP_GPIO12 MCPWM0_2A |
Deep-sleep wakeable LP GPIO12 (3.3V max, NOT 5V tolerant)
|
| 17 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 18 | IO4 GPIO4 | mixed | GPIO4 ADC1_CH3 FSPICLK MTCK LEDC_CH4 |
[INFO] Dedicated JTAG MTCK pin if external JTAG source is selected via GPIO25
Free for ADC1_CH3, direct IO_MUX SPI2 SCK, or GPIO when debugging via native USB Serial/JTAG.
Digital/Analog GPIO4, 12-bit ADC1_CH3, direct IO_MUX SPI2 SCK (FSPICLK), and JTAG MTCK
|
| 19 | IO5 GPIO5 | mixed | GPIO5 ADC1_CH4 FSPID MTDI LEDC_CH5 |
[INFO] Dedicated JTAG MTDI pin if external JTAG source is selected via GPIO25
Free for ADC1_CH4, direct IO_MUX SPI2 MOSI, or GPIO when debugging via native USB Serial/JTAG.
Digital/Analog GPIO5, 12-bit ADC1_CH4, direct IO_MUX SPI2 MOSI (FSPID), and JTAG MTDI
|
| 20 | IO10 GPIO10 | mixed | GPIO10 ZCD0 LP_GPIO10 MCPWM0_1A |
Deep-sleep wakeable LP GPIO10 and Analog Comparator Ref / Zero-Cross Detector 0 (ZCD0)
|
| 21 | IO11 GPIO11 | mixed | GPIO11 ZCD1 LP_GPIO11 MCPWM0_1B |
Deep-sleep wakeable LP GPIO11 and Analog Comparator Input / Zero-Cross Detector 1 (ZCD1)
|
| 22 | IO8 GPIO8 | digital | GPIO8 LP_GPIO8 MCPWM0_0A |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — MUST be HIGH for Download Boot)
Sampled at reset with no internal pull-up. Entering Joint Download Boot (GPIO9=LOW) requires GPIO8=HIGH (GPIO8=0 & GPIO9=0 is invalid). Add a 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Deep-sleep wakeable LP GPIO8 (Download Boot gate & ROM UART0 print strapping pin)
|
| 23 | IO9 GPIO9 | digital | GPIO9 LP_GPIO9 MCPWM0_0B |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=Download Boot)
Sampled at reset with internal weak pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters Joint Download Boot (USB Serial/JTAG + UART0).
Deep-sleep wakeable LP GPIO9 (BOOT button strapping pin with internal weak pull-up)
|
| 24 | IO22 GPIO22 | digital | GPIO22 LEDC_CH1 |
Digital GPIO22 (3.3V max, NOT 5V tolerant)
|
| 25 | IO25 GPIO25 | digital | GPIO25 FSPICS3 LEDC_CH4 |
[CAUTION] JTAG signal-source strapping pin (floating at reset — HIGH=USB JTAG, LOW=Pad JTAG)
Sampled at reset with NO internal pull resistor when EFUSE_DIS_PAD_JTAG=0 & EFUSE_USB_JTAG_SEL=1. Avoid external circuits pulling GPIO25 low at reset if native USB JTAG debugging is desired.
Digital GPIO25, FSPICS3, and JTAG source-selection strapping pin
|
| 26 | IO26 GPIO26 | special | GPIO26 USB_D- FSPICS4 LEDC_CH5 |
[CAUTION] Native Full-Speed USB Serial/JTAG D− differential line (40 mA max drive)
Enabled by default as USB D− for flashing, CDC console, and JTAG debugging. Reconfiguring GPIO26 as digital I/O disconnects native USB until reset.
Native USB 2.0 Full-Speed Serial/JTAG D− pad / Digital GPIO26
|
| 27 | IO27 GPIO27 | special | GPIO27 USB_D+ FSPICS5 LEDC_CH0 |
[CAUTION] Native Full-Speed USB Serial/JTAG D+ line (internal 1.5 kΩ USB pull-up active at reset)
Enabled by default with an internal USB D+ pull-up to 3.3V at reset. Reconfiguring GPIO27 as digital I/O disconnects native USB Serial/JTAG.
Native USB 2.0 Full-Speed Serial/JTAG D+ pad / Digital GPIO27
|
| 28 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 29 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 30 | RXD0 GPIO23 | digital | GPIO23 U0RXD FSPICS1 LEDC_CH2 |
[INFO] Default ROM bootloader UART0 RX input
Used by the ROM serial bootloader alongside USB Serial/JTAG in Download Boot mode. Freely usable after boot.
Digital GPIO23, default UART0 RX (U0RXD), and FSPICS1
|
| 31 | TXD0 GPIO24 | digital | GPIO24 U0TXD FSPICS2 LEDC_CH3 |
[INFO] Default ROM bootloader UART0 TX output (emits boot log at reset)
Outputs ROM diagnostic messages at reset unless suppressed by GPIO8. Freely usable after boot.
Digital GPIO24, default UART0 TX (U0TXD), and FSPICS2
|
| 32 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 33 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 34 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 35 | NC | nc | — |
No internal connection — leave floating on host PCB
|
| 36-53 | GND | ground | GND |
Underside LGA shield-return & central 3×3 exposed thermal ground pad array (Pins 36–53, 0V)
|