Espressif's ESP32-H2 omits Wi-Fi to optimize ultra-low-power Bluetooth 5.3 LE and IEEE 802.15.4 (Thread 1.3, Zigbee 3.0, Matter over Thread) end-node designs around a 96 MHz 32-bit RISC-V core, 320 KB SRAM (including 4 KB Deep-sleep LP memory), 128 KB ROM, and 2 MB or 4 MB of stacked Quad SPI flash in a 4×4 mm QFN-32 package. Clocked from a 32 MHz crystal (with separate VBAT RTC domain), its GPIO Matrix routes 2× UART, SPI2, 2× I2C, I2S0, TWAI (CAN), LEDC, MCPWM, and PARLIO across 19 exposed GPIOs plus native USB Serial/JTAG on GPIO26/GPIO27. Five 12-bit SAR ADC1 channels span GPIO1–GPIO5 alongside an analog zero-cross comparator on GPIO10/GPIO11. All I/Os are strictly 3.3 V non-5V-tolerant, and GPIO8/GPIO9/GPIO25 strapping rules apply.
Quad SPI XIP flash is stacked inside all ESP32-H2FH2/FH4 packages; GPIO6/GPIO7 and GPIO15–GPIO21 are not bonded externally.
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| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | VDD3P3 | power | VDD3P3 |
Analog & RF power supply (3.0V–3.6V, 3.3V nominal)
|
| 2 | VDD3P3 | power | VDD3P3 |
Analog & RF power supply (3.0V–3.6V, 3.3V nominal)
|
| 3 | GPIO0 | digital | GPIO0 FSPIQ LEDC_CH0 |
Digital GPIO0 (no ADC on ESP32-H2 — ADC1 starts at GPIO1) and direct IO_MUX SPI2 MISO (FSPIQ)
|
| 4 | GPIO1 | mixed | GPIO1 ADC1_CH0 FSPICS0 LEDC_CH1 |
Digital/Analog GPIO1, 12-bit ADC1_CH0, and direct IO_MUX SPI2 CS0 (FSPICS0) (3.3V max, NOT 5V tolerant)
|
| 5 | GPIO2 | mixed | GPIO2 ADC1_CH1 FSPIWP MTMS LEDC_CH2 |
[INFO] Dedicated JTAG MTMS pin if external JTAG source is selected via GPIO25
Free for ADC1_CH1, SPI2, or GPIO when debugging via native USB Serial/JTAG (GPIO26/GPIO27).
Digital/Analog GPIO2, 12-bit ADC1_CH1, FSPIWP, and JTAG MTMS
|
| 6 | GPIO3 | mixed | GPIO3 ADC1_CH2 FSPIHD MTDO LEDC_CH3 |
[INFO] Dedicated JTAG MTDO pin if external JTAG source is selected via GPIO25
Free for ADC1_CH2, SPI2, or GPIO when debugging via native USB Serial/JTAG.
Digital/Analog GPIO3, 12-bit ADC1_CH2, FSPIHD, and JTAG MTDO
|
| 7 | GPIO4 | mixed | GPIO4 ADC1_CH3 FSPICLK MTCK LEDC_CH4 |
[INFO] Dedicated JTAG MTCK pin if external JTAG source is selected via GPIO25
Free for ADC1_CH3, direct IO_MUX SPI2 SCK, or GPIO when debugging via native USB Serial/JTAG.
Digital/Analog GPIO4, 12-bit ADC1_CH3, direct IO_MUX SPI2 SCK (FSPICLK), and JTAG MTCK
|
| 8 | GPIO5 | mixed | GPIO5 ADC1_CH4 FSPID MTDI LEDC_CH5 |
[INFO] Dedicated JTAG MTDI pin if external JTAG source is selected via GPIO25
Free for ADC1_CH4, direct IO_MUX SPI2 MOSI, or GPIO when debugging via native USB Serial/JTAG.
Digital/Analog GPIO5, 12-bit ADC1_CH4, direct IO_MUX SPI2 MOSI (FSPID), and JTAG MTDI
|
| 9 | VDDPST1 | power | VDDPST1 |
Digital I/O power supply domain 1 for GPIO0–GPIO12 (3.0V–3.6V)
|
| 10 | GPIO8 | digital | GPIO8 LP_GPIO8 MCPWM0_0A |
[CAUTION] Boot mode & ROM log strapping pin (floating at reset — MUST be HIGH for Download Boot)
Sampled at reset with no internal pull-up. Entering Joint Download Boot (GPIO9=LOW) requires GPIO8=HIGH (GPIO8=0 & GPIO9=0 is invalid). Add a 10 kΩ pull-up if external circuitry could pull GPIO8 low at reset.
Deep-sleep wakeable LP GPIO8 (Download Boot gate & ROM UART0 print strapping pin)
|
| 11 | GPIO9 | digital | GPIO9 LP_GPIO9 MCPWM0_0B |
[CAUTION] Boot mode strapping pin (weak internal pull-up: HIGH=SPI Boot, LOW=Download Boot)
Sampled at reset with internal weak pull-up enabled. Pulling GPIO9 LOW during reset while GPIO8=HIGH enters Joint Download Boot (USB Serial/JTAG + UART0).
Deep-sleep wakeable LP GPIO9 (BOOT button strapping pin with internal weak pull-up)
|
| 12 | GPIO10 | mixed | GPIO10 ZCD0 LP_GPIO10 MCPWM0_1A |
Deep-sleep wakeable LP GPIO10 and Analog Comparator Ref / Zero-Cross Detector 0 (ZCD0)
|
| 13 | GPIO11 | mixed | GPIO11 ZCD1 LP_GPIO11 MCPWM0_1B |
Deep-sleep wakeable LP GPIO11 and Analog Comparator Input / Zero-Cross Detector 1 (ZCD1)
|
| 14 | GPIO12 | digital | GPIO12 LP_GPIO12 MCPWM0_2A |
Deep-sleep wakeable LP GPIO12 (3.3V max, NOT 5V tolerant)
|
| 15 | GPIO13 | digital | GPIO13 XTAL_32K_P LP_GPIO13 MCPWM0_2B |
Deep-sleep wakeable LP GPIO13 (VBAT domain) and optional 32.768 kHz RTC crystal P
|
| 16 | GPIO14 | digital | GPIO14 XTAL_32K_N LP_GPIO14 LEDC_CH0 |
Deep-sleep wakeable LP GPIO14 (VBAT domain) and optional 32.768 kHz RTC crystal N
|
| 17 | CHIP_EN CHIP_PU | reset | CHIP_EN |
[CAUTION] Active-HIGH chip enable/reset — never leave floating
High enables chip; Low powers off chip. Add an external RC delay circuit (10 kΩ pull-up to 3.3V and 1 µF capacitor to GND).
High-enable / active-low chip reset input (CHIP_EN / EN)
|
| 18 | VBAT | power | VBAT |
Battery / LP & RTC domain power supply (3.0V–3.6V; tie to 3V3 if coin-cell backup is unused)
|
| 19 | VDDA_PMU | power | VDDA_PMU |
Analog power supply for internal Power Management Unit (3.0V–3.6V)
|
| 20 | VDDPST2 | power | VDDPST2 |
Digital I/O power supply domain 2 for GPIO22–GPIO27 (3.0V–3.6V)
|
| 21 | GPIO22 | digital | GPIO22 LEDC_CH1 |
Digital GPIO22 (3.3V max, NOT 5V tolerant)
|
| 22 | U0RXD GPIO23 | digital | GPIO23 U0RXD FSPICS1 LEDC_CH2 |
[INFO] Default ROM bootloader UART0 RX input
Used by the ROM serial bootloader alongside USB Serial/JTAG in Download Boot mode. Freely usable after boot.
Digital GPIO23, default UART0 RX (U0RXD), and FSPICS1
|
| 23 | U0TXD GPIO24 | digital | GPIO24 U0TXD FSPICS2 LEDC_CH3 |
[INFO] Default ROM bootloader UART0 TX output (emits boot log at reset)
Outputs ROM diagnostic messages at reset unless suppressed by GPIO8. Freely usable after boot.
Digital GPIO24, default UART0 TX (U0TXD), and FSPICS2
|
| 24 | GPIO25 | digital | GPIO25 FSPICS3 LEDC_CH4 |
[CAUTION] JTAG signal-source strapping pin (floating at reset — HIGH=USB JTAG, LOW=Pad JTAG)
Sampled at reset with NO internal pull resistor when EFUSE_DIS_PAD_JTAG=0 & EFUSE_USB_JTAG_SEL=1. Avoid external circuits pulling GPIO25 low at reset if native USB JTAG debugging is desired.
Digital GPIO25, FSPICS3, and JTAG source-selection strapping pin
|
| 25 | GPIO26 | special | GPIO26 USB_D- FSPICS4 LEDC_CH5 |
[CAUTION] Native Full-Speed USB Serial/JTAG D− differential line (40 mA max drive)
Enabled by default as USB D− for flashing, CDC console, and JTAG debugging. Reconfiguring GPIO26 as digital I/O disconnects native USB until reset.
Native USB 2.0 Full-Speed Serial/JTAG D− pad / Digital GPIO26
|
| 26 | GPIO27 | special | GPIO27 USB_D+ FSPICS5 LEDC_CH0 |
[CAUTION] Native Full-Speed USB Serial/JTAG D+ line (internal 1.5 kΩ USB pull-up active at reset)
Enabled by default with an internal USB D+ pull-up to 3.3V at reset. Reconfiguring GPIO27 as digital I/O disconnects native USB Serial/JTAG.
Native USB 2.0 Full-Speed Serial/JTAG D+ pad / Digital GPIO27
|
| 27 | VDD3P3 | power | VDD3P3 |
Analog & RF power supply (3.0V–3.6V, 3.3V nominal)
|
| 28 | XTAL_N | clock | XTAL_N |
[INFO] 32 MHz RF reference crystal negative pin (32 MHz — NOT 40 MHz!)
Dedicated 32 MHz ±10 ppm crystal oscillator pin required for BLE 5.3 and IEEE 802.15.4 operation.
External 32 MHz crystal oscillator negative terminal
|
| 29 | XTAL_P | clock | XTAL_P |
[INFO] 32 MHz RF reference crystal positive pin (32 MHz — NOT 40 MHz!)
Dedicated 32 MHz ±10 ppm crystal oscillator pin required for BLE 5.3 and IEEE 802.15.4 operation.
External 32 MHz crystal oscillator positive terminal
|
| 30 | VDD3P3 | power | VDD3P3 |
Analog & RF power supply (3.0V–3.6V, 3.3V nominal)
|
| 31 | VDD3P3 | power | VDD3P3 |
Analog & RF power supply (3.0V–3.6V, 3.3V nominal)
|
| 32 | ANT | special | ANT |
[INFO] 2.4 GHz 50Ω RF antenna port (BLE 5.3 & 802.15.4 — NO Wi-Fi)
Dedicated 2.4 GHz RF input/output for Bluetooth 5.3 LE and IEEE 802.15.4 (Thread/Zigbee/Matter). Requires external 50Ω matching network.
2.4 GHz RF antenna input/output pin
|
| 33 | GND | ground | GND |
Central exposed thermal and electrical ground pad (0V)
|