Raspberry Pi's RP2350 features dual boot-selectable 150 MHz Arm Cortex-M33 (with FPU, DSP, and Arm TrustZone) or open-hardware Hazard3 RV32IMAC RISC-V cores backed by 520 KB of ten-bank SRAM, OTP secure-boot storage, an on-chip 1.1 V switched-mode core regulator, and an XIP QMI flash/PSRAM controller (with 2 MB stacked flash on RP2354A/RP2354B). Three Programmable I/O (PIO) blocks (12 state machines), an 8-lane High-Speed Serial Transmit (HSTX) peripheral on GPIO12–19, 2× UART, 2× SPI, 2× I2C, and 24 PWM channels span 30 GPIOs on QFN-60 (RP2350A, 4× ADC on GPIO26–29) or 48 GPIOs on QFN-80 (RP2350B, 8× ADC on GPIO40–47). Digital FT pads tolerate 5 V inputs only while IOVDD is powered at ~3.3 V, whereas ADC STD pads are strictly 3.3 V max (non-5V-tolerant); stepping A2 exhibits internal pull-down erratum RP2350-E9 (fixed in A4).
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Full Pin Reference (61 Pins)
| Pin # | Label | Type | Functions | Warnings & Notes |
|---|---|---|---|---|
| 1 | IOVDD | power | 3V3_IO IOVDD |
Digital GPIO bank power supply (1.8V–3.3V nominal; must be powered ~3.3V for 5V-tolerant FT operation)
|
| 2 | GPIO0 | digital | GPIO0 SPI0_RX UART0_TX I2C0_SDA PWM0_A PIO0 PIO1 PIO2 QMI_CS1n USB_OVCUR_DET |
RP2350 Bank 0 GPIO0 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 3 | GPIO1 | digital | GPIO1 SPI0_CSn UART0_RX I2C0_SCL PWM0_B PIO0 PIO1 PIO2 TRACECLK USB_VBUS_DET |
RP2350 Bank 0 GPIO1 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 4 | GPIO2 | digital | GPIO2 SPI0_SCK UART0_CTS UART0_TX I2C1_SDA PWM1_A PIO0 PIO1 PIO2 TRACEDATA0 USB_VBUS_EN |
RP2350 Bank 0 GPIO2 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 5 | GPIO3 | digital | GPIO3 SPI0_TX UART0_RTS UART0_RX I2C1_SCL PWM1_B PIO0 PIO1 PIO2 TRACEDATA1 USB_OVCUR_DET |
RP2350 Bank 0 GPIO3 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 6 | DVDD | power | 1V1_CORE DVDD |
[INFO] 1.1V digital core logic supply
1.1V nominal core logic supply — connect externally to filtered VREG output or external 1.1V rail with local 100nF decoupling.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1679
1.1V digital core power supply
|
| 7 | GPIO4 | digital | GPIO4 SPI0_RX UART1_TX I2C0_SDA PWM2_A PIO0 PIO1 PIO2 TRACEDATA2 USB_VBUS_DET |
RP2350 Bank 0 GPIO4 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 8 | GPIO5 | digital | GPIO5 SPI0_CSn UART1_RX I2C0_SCL PWM2_B PIO0 PIO1 PIO2 TRACEDATA3 USB_VBUS_EN |
RP2350 Bank 0 GPIO5 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 9 | GPIO6 | digital | GPIO6 SPI0_SCK UART1_CTS UART1_TX I2C1_SDA PWM3_A PIO0 PIO1 PIO2 USB_OVCUR_DET |
RP2350 Bank 0 GPIO6 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 10 | GPIO7 | digital | GPIO7 SPI0_TX UART1_RTS UART1_RX I2C1_SCL PWM3_B PIO0 PIO1 PIO2 USB_VBUS_DET |
RP2350 Bank 0 GPIO7 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 11 | IOVDD | power | 3V3_IO IOVDD |
Digital GPIO bank power supply (1.8V–3.3V nominal; must be powered ~3.3V for 5V-tolerant FT operation)
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| 12 | GPIO8 | digital | GPIO8 SPI1_RX UART1_TX I2C0_SDA PWM4_A PIO0 PIO1 PIO2 QMI_CS1n USB_VBUS_EN |
RP2350 Bank 0 GPIO8 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
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| 13 | GPIO9 | digital | GPIO9 SPI1_CSn UART1_RX I2C0_SCL PWM4_B PIO0 PIO1 PIO2 USB_OVCUR_DET |
RP2350 Bank 0 GPIO9 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
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| 14 | GPIO10 | digital | GPIO10 SPI1_SCK UART1_CTS UART1_TX I2C1_SDA PWM5_A PIO0 PIO1 PIO2 USB_VBUS_DET |
RP2350 Bank 0 GPIO10 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 15 | GPIO11 | digital | GPIO11 SPI1_TX UART1_RTS UART1_RX I2C1_SCL PWM5_B PIO0 PIO1 PIO2 USB_VBUS_EN |
RP2350 Bank 0 GPIO11 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 16 | GPIO12 | digital | GPIO12 HSTX0 SPI1_RX UART0_TX I2C0_SDA PWM6_A PIO0 PIO1 PIO2 CLOCK_GPIN0 USB_OVCUR_DET |
RP2350 Bank 0 GPIO12 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 17 | GPIO13 | digital | GPIO13 HSTX1 SPI1_CSn UART0_RX I2C0_SCL PWM6_B PIO0 PIO1 PIO2 CLOCK_GPOUT0 USB_VBUS_DET |
RP2350 Bank 0 GPIO13 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
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| 18 | GPIO14 | digital | GPIO14 HSTX2 SPI1_SCK UART0_CTS UART0_TX I2C1_SDA PWM7_A PIO0 PIO1 PIO2 CLOCK_GPIN1 USB_VBUS_EN |
RP2350 Bank 0 GPIO14 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
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| 19 | GPIO15 | digital | GPIO15 HSTX3 SPI1_TX UART0_RTS UART0_RX I2C1_SCL PWM7_B PIO0 PIO1 PIO2 CLOCK_GPOUT1 USB_OVCUR_DET |
RP2350 Bank 0 GPIO15 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 20 | IOVDD | power | 3V3_IO IOVDD |
Digital GPIO bank power supply (1.8V–3.3V nominal; must be powered ~3.3V for 5V-tolerant FT operation)
|
| 21 | XIN | clock | XIN |
[INFO] 12MHz crystal input or 1.8V–3.3V CMOS clock input
Crystal oscillator input (defaults to 12MHz for ROM USB bootloader; configurable via OTP) or single-ended CMOS clock input.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1676, Table 1686
Crystal oscillator / CMOS clock input
|
| 22 | XOUT | clock | XOUT |
[INFO] 12MHz crystal output (add 1kΩ series damping resistor)
Crystal oscillator output; place a 1kΩ series damping resistor for typical SMD crystals, or leave disconnected when driving XIN externally.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1676
Crystal oscillator output
|
| 23 | DVDD | power | 1V1_CORE DVDD |
[INFO] 1.1V digital core logic supply
1.1V nominal core logic supply — connect externally to filtered VREG output or external 1.1V rail with local 100nF decoupling.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1679
1.1V digital core power supply
|
| 24 | SWCLK | digital | SWCLK |
[INFO] Dedicated CoreSight SWD debug clock
Multi-drop Serial Wire Debug clock providing debug access to both Arm Cortex-M33 and Hazard3 RISC-V cores.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1677, Table 1687
Serial Wire Debug Clock
|
| 25 | SWDIO | digital | SWDIO |
[INFO] Dedicated CoreSight SWD debug data I/O
Multi-drop Serial Wire Debug bidirectional data line providing debug access to both Arm Cortex-M33 and Hazard3 RISC-V cores.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1677
Serial Wire Debug Data I/O
|
| 26 | RUN | reset | RUN |
[INFO] Active-low global hardware reset (pull LOW to reset RP2350)
Global asynchronous active-low reset pin. Drive LOW to reset RP2350; tie to IOVDD or pull HIGH via 10kΩ for normal operation.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1677
Global asynchronous active-low reset
|
| 27 | GPIO16 | digital | GPIO16 HSTX4 SPI0_RX UART0_TX I2C0_SDA PWM0_A PIO0 PIO1 PIO2 USB_VBUS_DET |
RP2350 Bank 0 GPIO16 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 28 | GPIO17 | digital | GPIO17 HSTX5 SPI0_CSn UART0_RX I2C0_SCL PWM0_B PIO0 PIO1 PIO2 USB_VBUS_EN |
RP2350 Bank 0 GPIO17 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 29 | GPIO18 | digital | GPIO18 HSTX6 SPI0_SCK UART0_CTS UART0_TX I2C1_SDA PWM1_A PIO0 PIO1 PIO2 USB_OVCUR_DET |
RP2350 Bank 0 GPIO18 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 30 | IOVDD | power | 3V3_IO IOVDD |
Digital GPIO bank power supply (1.8V–3.3V nominal; must be powered ~3.3V for 5V-tolerant FT operation)
|
| 31 | GPIO19 | digital | GPIO19 HSTX7 SPI0_TX UART0_RTS UART0_RX I2C1_SCL PWM1_B PIO0 PIO1 PIO2 QMI_CS1n USB_VBUS_DET |
RP2350 Bank 0 GPIO19 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 32 | GPIO20 | digital | GPIO20 SPI0_RX UART1_TX I2C0_SDA PWM2_A PIO0 PIO1 PIO2 CLOCK_GPIN0 USB_VBUS_EN |
RP2350 Bank 0 GPIO20 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 33 | GPIO21 | digital | GPIO21 SPI0_CSn UART1_RX I2C0_SCL PWM2_B PIO0 PIO1 PIO2 CLOCK_GPOUT0 USB_OVCUR_DET |
RP2350 Bank 0 GPIO21 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
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| 34 | GPIO22 | digital | GPIO22 SPI0_SCK UART1_CTS UART1_TX I2C1_SDA PWM3_A PIO0 PIO1 PIO2 CLOCK_GPIN1 USB_VBUS_DET |
RP2350 Bank 0 GPIO22 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 35 | GPIO23 | digital | GPIO23 SPI0_TX UART1_RTS UART1_RX I2C1_SCL PWM3_B PIO0 PIO1 PIO2 CLOCK_GPOUT1 USB_VBUS_EN |
RP2350 Bank 0 GPIO23 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 36 | GPIO24 | digital | GPIO24 SPI1_RX UART1_TX I2C0_SDA PWM4_A PIO0 PIO1 PIO2 CLOCK_GPOUT2 USB_OVCUR_DET |
RP2350 Bank 0 GPIO24 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
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| 37 | GPIO25 | digital | GPIO25 SPI1_CSn UART1_RX I2C0_SCL PWM4_B PIO0 PIO1 PIO2 CLOCK_GPOUT3 USB_VBUS_DET |
RP2350 Bank 0 GPIO25 (FT pad: 5V-tolerant up to 5.5V ONLY while IOVDD is powered at ~3.3V; max 3.63V when unpowered; stepping A2 erratum RP2350-E9 on internal pull-downs, fixed in A3)
|
| 38 | IOVDD | power | 3V3_IO IOVDD |
Digital GPIO bank power supply (1.8V–3.3V nominal; must be powered ~3.3V for 5V-tolerant FT operation)
|
| 39 | DVDD | power | 1V1_CORE DVDD |
[INFO] 1.1V digital core logic supply
1.1V nominal core logic supply — connect externally to filtered VREG output or external 1.1V rail with local 100nF decoupling.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1679
1.1V digital core power supply
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| 40 | GPIO26 | mixed | ADC0 GPIO26 SPI1_SCK UART1_CTS UART1_TX I2C1_SDA PWM5_A PIO0 PIO1 PIO2 USB_VBUS_EN |
[CAUTION] ADC pad — strictly NOT 5V tolerant (3.63V max, ESD diode to IOVDD)
Unlike RP2350 digital FT pads, ADC-capable STD pads (GPIO26–29 on RP2350A; GPIO40–47 on RP2350B) incorporate an ESD clamp diode to IOVDD and are strictly NOT 5V tolerant (3.63V max; do not drive while unpowered). Disable the digital input buffer in firmware when sampling ADC, and note stepping A2 erratum RP2350-E9.
Ref: RP2350 Datasheet §14.8.2 Table 1674, §14.9.1 Table 1680; Appendix D.5.1 RP2350-E9
RP2350A ADC input 0 / GPIO26 (STD pad with ESD diode to IOVDD — strictly NOT 5V tolerant, 3.63V max)
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| 41 | GPIO27 | mixed | ADC1 GPIO27 SPI1_TX UART1_RTS UART1_RX I2C1_SCL PWM5_B PIO0 PIO1 PIO2 USB_OVCUR_DET |
[CAUTION] ADC pad — strictly NOT 5V tolerant (3.63V max, ESD diode to IOVDD)
Unlike RP2350 digital FT pads, ADC-capable STD pads (GPIO26–29 on RP2350A; GPIO40–47 on RP2350B) incorporate an ESD clamp diode to IOVDD and are strictly NOT 5V tolerant (3.63V max; do not drive while unpowered). Disable the digital input buffer in firmware when sampling ADC, and note stepping A2 erratum RP2350-E9.
Ref: RP2350 Datasheet §14.8.2 Table 1674, §14.9.1 Table 1680; Appendix D.5.1 RP2350-E9
RP2350A ADC input 1 / GPIO27 (STD pad with ESD diode to IOVDD — strictly NOT 5V tolerant, 3.63V max)
|
| 42 | GPIO28 | mixed | ADC2 GPIO28 SPI1_RX UART0_TX I2C0_SDA PWM6_A PIO0 PIO1 PIO2 USB_VBUS_DET |
[CAUTION] ADC pad — strictly NOT 5V tolerant (3.63V max, ESD diode to IOVDD)
Unlike RP2350 digital FT pads, ADC-capable STD pads (GPIO26–29 on RP2350A; GPIO40–47 on RP2350B) incorporate an ESD clamp diode to IOVDD and are strictly NOT 5V tolerant (3.63V max; do not drive while unpowered). Disable the digital input buffer in firmware when sampling ADC, and note stepping A2 erratum RP2350-E9.
Ref: RP2350 Datasheet §14.8.2 Table 1674, §14.9.1 Table 1680; Appendix D.5.1 RP2350-E9
RP2350A ADC input 2 / GPIO28 (STD pad with ESD diode to IOVDD — strictly NOT 5V tolerant, 3.63V max)
|
| 43 | GPIO29 | mixed | ADC3 GPIO29 SPI1_CSn UART0_RX I2C0_SCL PWM6_B PIO0 PIO1 PIO2 USB_VBUS_EN |
[CAUTION] ADC pad — strictly NOT 5V tolerant (3.63V max, ESD diode to IOVDD)
Unlike RP2350 digital FT pads, ADC-capable STD pads (GPIO26–29 on RP2350A; GPIO40–47 on RP2350B) incorporate an ESD clamp diode to IOVDD and are strictly NOT 5V tolerant (3.63V max; do not drive while unpowered). Disable the digital input buffer in firmware when sampling ADC, and note stepping A2 erratum RP2350-E9.
Ref: RP2350 Datasheet §14.8.2 Table 1674, §14.9.1 Table 1680; Appendix D.5.1 RP2350-E9
RP2350A ADC input 3 / GPIO29 (STD pad with ESD diode to IOVDD — strictly NOT 5V tolerant, 3.63V max)
|
| 44 | ADC_AVDD | power | ADC_AVDD |
12-bit SAR ADC analog power supply and reference (3.3V nominal)
|
| 45 | IOVDD | power | 3V3_IO IOVDD |
Digital GPIO bank power supply (1.8V–3.3V nominal; must be powered ~3.3V for 5V-tolerant FT operation)
|
| 46 | VREG_AVDD | power | VREG_AVDD |
[INFO] Internal core regulator 3.3V analog supply
Analog control power supply for internal 1.1V core switching regulator (3.3V nominal).
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1679
Analog power supply for internal 1.1V core voltage regulator (3.3V nominal)
|
| 47 | VREG_PGND | ground | VREG_PGND |
Power-ground return for internal 1.1V core switching regulator (tie directly to GND)
|
| 48 | VREG_LX | special | VREG_LX |
[CAUTION] Core SMPS switch output — requires external 3.3µH inductor to 1.1V DVDD
Switched-mode 1.1V output (up to 200mA) for internal core regulator; connect to low-DCR 3.3µH power inductor and output capacitor feeding DVDD/VREG_FB.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1679
Switched-mode inductor node for internal 1.1V core voltage regulator (max 200mA)
|
| 49 | VREG_VIN | power | VREG_VIN |
[INFO] Internal core SMPS power input (2.7V–5.5V nominal)
Power stage input for the internal 1.1V core buck regulator (2.7V to 5.5V; decouple closely to VREG_PGND with 4.7µF MLCC).
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1679
Power input for internal 1.1V core voltage regulator (2.7V–5.5V nominal)
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| 50 | VREG_FB | special | VREG_FB |
[INFO] Core SMPS 1.1V feedback sense input
Voltage feedback sense pin for the internal 1.1V core regulator; connect directly to the filtered 1.1V output capacitor / DVDD rail.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1679
1.1V voltage feedback sense input for internal core regulator
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| 51 | USB_DM | special | USB_DM |
[CAUTION] Requires external 27Ω series termination resistor
USB Full/Low-Speed differential D- signal (can also operate as Bank 1 software GPIO/UART/I2C if USB is unused). Requires external 27Ω series termination resistor.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1678
USB full-speed differential D- signal
|
| 52 | USB_DP | special | USB_DP |
[CAUTION] Requires external 27Ω series termination resistor
USB Full/Low-Speed differential D+ signal (can also operate as Bank 1 software GPIO/UART/I2C if USB is unused). Requires external 27Ω series termination resistor.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1678
USB full-speed differential D+ signal
|
| 53 | USB_OTP_VDD | power | USB_OTP_VDD |
3.3V power supply for internal USB Full-Speed PHY and OTP memory
|
| 54 | QSPI_IOVDD | power | QSPI_IOVDD |
Dedicated I/O supply for QSPI XIP flash/PSRAM bank (1.8V–3.3V nominal)
|
| 55 | QSPI_SD3 | digital | QSPI_SD3 |
[CAUTION] Dedicated XIP QSPI flash/PSRAM bus (internal 2MB flash on RP2354)
Primary QMI execute-in-place QSPI flash/PSRAM interface (bonded internally to 2MB stacked QSPI flash on RP2354A/RP2354B; Bank 1 GPIO available only when XIP flash is unused).
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1675
Dedicated QMI XIP QSPI flash/PSRAM signal QSPI_SD3
|
| 56 | QSPI_SCLK | digital | QSPI_SCLK |
[CAUTION] Dedicated XIP QSPI flash/PSRAM bus (internal 2MB flash on RP2354)
Primary QMI execute-in-place QSPI flash/PSRAM interface (bonded internally to 2MB stacked QSPI flash on RP2354A/RP2354B; Bank 1 GPIO available only when XIP flash is unused).
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1675
Dedicated QMI XIP QSPI flash/PSRAM signal QSPI_SCLK
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| 57 | QSPI_SD0 | digital | QSPI_SD0 |
[CAUTION] Dedicated XIP QSPI flash/PSRAM bus (internal 2MB flash on RP2354)
Primary QMI execute-in-place QSPI flash/PSRAM interface (bonded internally to 2MB stacked QSPI flash on RP2354A/RP2354B; Bank 1 GPIO available only when XIP flash is unused).
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1675
Dedicated QMI XIP QSPI flash/PSRAM signal QSPI_SD0
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| 58 | QSPI_SD2 | digital | QSPI_SD2 |
[CAUTION] Dedicated XIP QSPI flash/PSRAM bus (internal 2MB flash on RP2354)
Primary QMI execute-in-place QSPI flash/PSRAM interface (bonded internally to 2MB stacked QSPI flash on RP2354A/RP2354B; Bank 1 GPIO available only when XIP flash is unused).
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1675
Dedicated QMI XIP QSPI flash/PSRAM signal QSPI_SD2
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| 59 | QSPI_SD1 | digital | QSPI_SD1 |
[CAUTION] Dedicated XIP QSPI flash/PSRAM bus (internal 2MB flash on RP2354)
Primary QMI execute-in-place QSPI flash/PSRAM interface (bonded internally to 2MB stacked QSPI flash on RP2354A/RP2354B; Bank 1 GPIO available only when XIP flash is unused).
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1675
Dedicated QMI XIP QSPI flash/PSRAM signal QSPI_SD1
|
| 60 | QSPI_SS | digital | QSPI_SS |
[CAUTION] Boot strapping pin (BOOTSEL) & QSPI Flash CS#
Sampled at reset: pulling QSPI_SS LOW forces ROM UF2/PICOBOOT USB/UART bootloader mode instead of booting from QSPI flash.
Ref: RP2350 Datasheet §1.2.2 Table 2, §14.8.2 Table 1675
QSPI Flash Chip Select / Boot strapping pin (BOOTSEL)
|
| 61 | GND | ground | GND |
Central exposed thermal and electrical ground pad
|